Field Bus Driver Circuit With Switchable Cascode Stages for EMC
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Solution Overview
Problem
In field bus systems like CAN or FlexRay, signal reflections due to impedance mismatches and high input capacitance in bus driver circuits lead to signal integrity issues at higher data rates, particularly when semiconductor technologies restrict symmetric cascode stage and diode connections, resulting in unsymmetric input capacitances and compromised EMC performance.
Innovation Solution
A transmitter circuit for a field bus driver with switchable cascode stages, where control circuitry generates specific drive signals to switch transistors on and off based on data signals, incorporating a delay mechanism to manage cascode stage activation and deactivation, and a compensation circuit to reduce common mode voltage disturbances, allowing for unsymmetric input capacitances and improved EMC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the cascode stage is contacted directly to the bus terminal to reduce input capacitance, then the input capacitance is reduced, but the input capacitances of the two differential bus terminals become unsymmetric which negatively impacts EMC performance
Solution Approach 1:
The patent implements dynamic switching of the cascode stage connection configuration. A switching circuit is introduced that can change the connection topology between the cascode stage and bus terminals based on operational requirements. This allows the system to switch between symmetric and asymmetric configurations, resolving the contradiction by making the capacitance balance dynamic rather than fixed.
Solution Approach 2:
The patent changes the connection parameters of the cascode stage dynamically. By using control signals to adjust the switching state of transistors in the switching circuit, the electrical connection parameters (symmetry/asymmetry) are changed based on the operational mode, allowing optimization of both input capacitance and EMC performance under different conditions.
2Reliability
If the cascode stage is kept permanently switched on to ensure signal integrity, then signal integrity is maintained, but the input capacitance remains high causing delays in signal propagation
Solution Approach 1:
The patent transitions from a static permanently-on cascode stage to a dynamically controllable configuration. The switching circuit enables the cascode stage to be switched on or off based on the data transmission state, reducing input capacitance during reception while maintaining signal integrity during transmission.
Solution Approach 2:
The patent implements periodic switching of the cascode stage based on the transmission/reception cycle. The cascode stage is activated during transmission periods to ensure signal integrity and deactivated during reception periods to reduce input capacitance, creating a periodic action pattern that resolves the contradiction.
3Reliability
If symmetric connection of cascode stages is implemented to improve EMC performance, then EMC performance is improved, but input capacitance cannot be effectively reduced
Solution Approach 1:
The patent intentionally introduces asymmetric connection configurations for the cascode stages through the switching circuit. During transmission mode, the asymmetric configuration allows effective reduction of input capacitance while the controlled switching ensures EMC performance is maintained through proper timing and signal coordination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces input capacitance and enhances signal integrity and EMC performance by dynamically controlling cascode stages and compensating for common mode voltage disturbances, addressing the limitations of existing semiconductor technologies.
Implementation Method 1
The first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor. The control circuitry is configured to generate first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor
Implementation Method 2
the second transistor and the fourth transistor are switched off when the transmit signal indicates a recessive bus state and a specific first delay time has lapsed since the transmit signal indicating a transition from a dominant to a recessive bus state
Data Source
AI summary
A transmitter circuit for a field bus driver includes a first bus terminal and a second bus terminal for connecting a first bus line and, respectively, a second bus line. The transmitter circuit further includes a first supply terminal for receiving a supply voltage and second supply terminal for receiving a reference voltage, a first switching circuit coupled between the first supply terminal and the first bus terminal, and a second switching circuit coupled between the second bus terminal and the second supply terminal. The first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor. Further, the transmitter circuit comprises control circuitry configured to generate first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor based on a transmit signal.