Field Device Memory Soundness Verification via Duplicate Buffer Comparison

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Solution Overview

Problem

Field devices, such as Coriolis flowmeters, face challenges in verifying the soundness of memory areas where values dynamically change during operation, making it difficult to ensure memory integrity.

Innovation Solution

Implementing a calculation result comparator that uses two signal processing programs to temporarily store and compare calculation results in different buffer areas, allowing for the detection of anomalies and ensuring memory soundness by matching results from static and dynamic areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory areas are used to store dynamically changing calculation results during operation, then calculation functionality is improved, but memory soundness verification becomes difficult

Engineering Contradiction:
Improvecalculation functionalityVSAvoidmemory soundness verification
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent creates a duplicate copy of the calculation result storage buffer area. Two identical buffer areas are provided, each capable of storing calculation results independently. By copying results to both buffers and comparing them, the system can verify memory soundness without compromising calculation functionality.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent implements a feedback mechanism where calculation results are written to duplicate buffer areas and then compared. The comparison result feeds back into the system to determine whether memory is functioning correctly, enabling continuous verification during operation.

Inventive Principle:
Principle #23Feedback

2Reliability

If duplicate buffer areas are provided for memory verification, then memory soundness verification is improved, but device complexity increases

Engineering Contradiction:
Improvememory soundness verificationVSAvoidbuffer area configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the verification function with the existing calculation result storage function. The duplicate buffer areas serve dual purposes: storing calculation results during normal operation and enabling verification through comparison. This merging approach avoids adding separate verification hardware.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP2857805B1Field device
Publication Date: 2020.03.25 YOKOGAWA ELECTRIC CORP
  • EP2857805B1 patent drawingFigure 1
  • EP2857805B1 patent drawingFigure 2
  • EP2857805B1 patent drawingFigure 3

AI summary

A field device includes a first program area storing a first program, a second program area storing a second program designed such that if a program execution portion executes each of the first and second programs using the same data, a result of a calculation performed according to the second program is the same as a result of a calculation performed according to the first program, a first calculation result storage buffer storing a result of the calculation performed by the program execution portion according to the first program, and a second calculation result storage buffer storing a result of the calculation performed by the program execution portion according to the second program, and a calculation result comparator comparing the calculation result stored in the first calculation result storage buffer with the calculation result stored in the second calculation result storage buffer.