Field Electrode Metallization Layout for Voltage Overshoot Control
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Solution Overview
Problem
Existing semiconductor devices with field electrodes in trenches face challenges in managing electrical resistance, particularly during switching events, where voltage overshoots can occur due to direct connections between metallization layers above the field electrode trench.
Innovation Solution
The implementation of a metallization structure with a lower and upper metallization layer separated by an insulating layer, where the first interconnect is laterally offset from the field electrode trench, increasing the conductor line length and resistance, thereby reducing voltage overshoots by avoiding direct connections above the field electrode trench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metallization layers are directly connected above the field electrode trench, then the electrical connection is short and resistance is low, but voltage overshoots occur during switching events
Solution Approach 1:
The patent transitions from a direct vertical connection (one-dimensional path) to an L-shaped path that extends laterally before connecting upward (two-dimensional path). The first interconnect extends laterally offset from the field electrode trench and then connects upward to the upper metallization layer, increasing the conductor line length and resistance to reduce voltage overshoots during switching events.
Solution Approach 2:
The first interconnect acts as an intermediary element between the lower and upper metallization layers. Instead of direct connection, the lateral extension of the first interconnect serves as a mediating structure that increases the electrical path length and introduces controlled resistance, thereby reducing voltage overshoots while maintaining electrical connectivity.
2Reliability
If the first interconnect is laterally offset from the field electrode trench, then the conductor line length and resistance are increased, but the device structure becomes more complex
Solution Approach 1:
The first interconnect is designed with an L-shaped configuration that extends laterally offset from the field electrode trench and then connects upward. This two-dimensional path increases the conductor line length and output resistance compared to a direct vertical connection, providing better control over voltage overshoots during switching events.
Solution Approach 2:
The patent modifies the geometric parameters of the interconnect structure by introducing a lateral offset distance and increasing the conductor line length. These parameter changes directly increase the electrical resistance of the connection path, which is used to control and reduce voltage overshoots during device operation.
3Reliability
If the lower and upper metallization layers are isolated by an insulating layer above the field electrode trench, then voltage overshoots are reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The space above the field electrode trench is segmented into isolated regions for the lower and upper metallization layers using an insulating layer. This segmentation prevents direct electrical connection between the metallization layers in this region, reducing voltage overshoots during switching events while allowing each layer to be independently configured.
Solution Approach 2:
The insulating layer serves as an intermediary barrier between the lower and upper metallization layers above the field electrode trench. This intermediate layer electrically isolates the two metallization layers, preventing direct connection and reducing voltage overshoots, while the first interconnect provides the necessary electrical connection through a lateral offset path.
Data Source
AI summary
The present application relates to a semiconductor device, including: a field electrode in a needle-shaped field electrode trench extending from a frontside of a semiconductor body into the semiconductor body; a lower metallization layer on the frontside of the semiconductor body and electrically connected to the field electrode; an insulating layer on the lower metallization layer; an upper metallization layer on the insulating layer, and a first interconnect electrically connecting the lower metallization layer to the upper metallization layer. The first interconnect is laterally offset to the field electrode trench. The lower metallization layer is not connected to the upper metallization layer in a region vertically above the field electrode trench.


