Multi-Processor Data Movement With Field-Encoded Routing Addresses
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Solution Overview
Problem
Existing multi-processing unit computing devices face challenges in efficiently supporting different types of transactions while maintaining a consistent memory map and optimizing data movement between host processors and accelerator processors.
Innovation Solution
Implementing a transfer address mechanism with a retarget address field, control fields, and a chip identifier field to route data and configuration transfers efficiently across multiple accelerator processors, enabling hardware-controlled data movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a consistent memory map is maintained across multiple accelerator processors, then memory mapping consistency is improved, but data movement efficiency may deteriorate due to increased routing complexity
Solution Approach 1:
The address space is segmented into different regions with specific fields (retarget address field, chip identifier field, control fields) to handle different types of transactions (configuration vs. dataflow) separately. This segmentation allows each region to be optimized for its specific purpose while maintaining overall consistency.
Solution Approach 2:
The transfer address mechanism acts as an intermediary between the host processor and accelerator processors. It includes intermediate fields (retarget address, chip identifier) that facilitate routing decisions and data movement coordination without requiring direct complex routing between all processors.
2Adaptability or versatility
If different types of transactions (configuration and dataflow) are supported simultaneously, then system versatility is improved, but transaction processing complexity worsens
Solution Approach 1:
Different fields within the transfer address are assigned specific qualities for different transaction types. The control fields contain specific bits (first control bit, second control bit) that have different meanings for configuration transfers versus dataflow transfers. This local differentiation allows the system to handle multiple transaction types with a unified address structure.
Solution Approach 2:
Instead of having separate address structures for different transaction types, the invention inverts the approach by using a unified address structure where the distinction between transaction types is made through specific control fields and interpretation rules, simplifying the overall architecture.
3Speed
If hardware-controlled data movement is implemented, then data transfer speed is improved, but control mechanism complexity worsens
Solution Approach 1:
The transfer address mechanism is designed to be self-interpreting by the hardware. The control fields, chip identifier field, and retarget address field automatically guide the routing and processing without requiring complex software intervention. The hardware itself services the data movement by interpreting the address fields and executing appropriate routing decisions.
Data Source
AI summary
Data movement techniques for multi-processor computing devices utilize a transfer address including a retarget address field, one or more control fields and a chip identifier field. The retarget address field identifies a dataspace of a host processor or given accelerator processors. The one or more control fields indicate a dataflow transfer or a configuration transfer. The chip identifier field indicates a destination accelerator processor. The transfer address can optional also include a flow identifier field indicating an applicable dataflow register for a dataflow transfer.