Field Insulating Layer Protrusion for Stable Source/Drain Contacts
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is the difficulty in forming source/drain contacts due to the decrease in capacitance as pitch size decreases, which affects electrical stability between contacts.
Innovation Solution
The solution involves forming a part of the field insulating layer on the element isolation region between NMOS and PMOS regions to protrude vertically, reducing the depth of the recess for forming the source/drain contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the pitch size is decreased to achieve high integration, then the device density is improved, but the capacitance decreases and electrical stability deteriorates
Solution Approach 1:
The patent introduces a vertical protrusion structure in the field insulating layer, transitioning from a planar configuration to a three-dimensional structure. This vertical dimension allows the source/drain contact to reach the active region more directly, compensating for the reduced horizontal pitch size and maintaining electrical stability despite higher device density.
2Area of moving object
If the pitch size is decreased to achieve high integration, then the device density is improved, but the manufacturing complexity increases
Solution Approach 1:
The protrusion structure of the field insulating layer is formed in advance during the manufacturing process, before the source/drain contact formation step. This preliminary action prepares the pathway for the contact, simplifying subsequent processing steps and reducing overall manufacturing complexity despite the increased device density.
3Ease of manufacture
If the recess depth is reduced by forming a protrusion in the field insulating layer, then the ease of manufacture is improved, but the structural complexity increases
Solution Approach 1:
The field insulating layer is modified locally by forming a protrusion only in the specific region between the NMOS and PMOS regions, while the rest of the field insulating layer maintains its original planar structure. This localized modification simplifies the source/drain contact formation process without requiring complex changes to the entire device structure.
Data Source
AI summary
A semiconductor device including a field insulating layer, which surrounds at least a part of side walls of each of first and second active patterns on a substrate, the field insulating layer including a protrusion protruding upwardly in a vertical direction between the first active pattern and second active pattern, respectively.