Field Limiting Ring Layout for SiC Breakdown Voltage Stability
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face challenges in achieving high breakdown voltage and reliability due to complex ion implantation overlaps and alignment issues in the field limiting ring (FLR) structure, leading to potential destruction and leak current problems, especially under high temperature and voltage conditions.
Innovation Solution
A semiconductor device with a field limiting ring (FLR) structure formed by concentrically arranged p-type regions in the edge termination region, where the impurity concentration and depth of the FLR regions are adjusted through multiple stages of ion implantation in the n-type epitaxial layers, allowing for easier alignment and deeper penetration, thereby reducing the risk of misalignment-induced destruction and enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If complex ion implantation overlaps are used to form the field limiting ring structure, then breakdown voltage is improved, but manufacturing precision deteriorates due to alignment issues
Solution Approach 1:
The field limiting ring structure is segmented into multiple discrete ion implantation regions arranged concentrically in the termination region. These segments can be formed through sequential implantation steps with simpler alignment requirements compared to forming a continuous complex overlap structure, thereby maintaining the voltage blocking capability while reducing alignment sensitivity.
Solution Approach 2:
The field limiting ring is positioned in the termination region at a different spatial location than the active device regions, utilizing the peripheral dimension of the semiconductor device. This dimensional separation allows the FLR to be formed with less stringent alignment requirements relative to the active devices, while still contributing to the overall breakdown voltage through its concentric arrangement.
2Strength
If deeper ion implantation is used to enhance voltage withstanding, then breakdown voltage is improved, but reliability worsens due to potential destruction from misalignment
Solution Approach 1:
The field limiting ring structure is designed and positioned in advance in the termination region, away from the active device areas. This preliminary positioning ensures that even with deeper implantation profiles, the misalignment risk is minimized because the FLR is formed in a dedicated region with its own reference framework, independent of the active device alignment.
Solution Approach 2:
The concentric arrangement of multiple ion implantation regions in the field limiting ring provides a buffer against misalignment effects. The distributed nature of these regions means that minor alignment variations are averaged out, providing a cushioning effect that protects device reliability even when deeper implantation is used to achieve higher breakdown voltage.
3Ease of manufacture
If ion implantation regions are arranged concentrically in the termination region, then ease of manufacture is improved, but device complexity increases
Solution Approach 1:
The concentrically arranged ion implantation regions in the field limiting ring serve multiple functions: they establish the voltage blocking capability in the termination region, provide reference markers for subsequent processing steps, and create a structured pattern that simplifies mask design and alignment for future implantation or deposition steps. This multi-functionality justifies the increased structural complexity by providing manufacturing benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a reliable and stable voltage withstanding structure with improved breakdown voltage and reduced susceptibility to misalignment, ensuring the semiconductor device operates effectively under high temperature and voltage conditions without increased leak current.
Implementation Method 1
a first-conductivity-type semiconductor device having a pn junction between a p-type region and an n-type region formed by ion implantation in an n-type epitaxial layer
Data Source
AI summary
A semiconductor substrate is fabricated in which only first and second n−-type epitaxial layers are stacked on an n+-type starting substrate, a front surface of the substrate being a continuously flat surface from an active region to a chip end. In an edge termination region, as a voltage withstanding structure, a ring-shape FLR is provided in which p-type FLR regions concentrically surrounding a periphery of the active region are disposed apart from one another. The p-type FLR regions each have a layered structure configured by multiple p-type regions (partial FLRs) that are adjacent to one another in a depth direction and formed by ion implantation of a p-type impurity for the first and the second n−-type epitaxial layers configuring the substrate. A predetermined breakdown voltage is obtained by adjusting the number of stacked layers and impurity concentrations of the partial FLRs of the p-type FLR regions.