Field Plate Gate Structures for High-Voltage MOSFETs
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Solution Overview
Problem
Current high-voltage MOSFETs for semiconductor devices face challenges in achieving increased breakdown voltage to meet the demands of advanced semiconductor fabrication, particularly in the design and operation of lateral double diffused metal-oxide-semiconductor (LDMOS) devices.
Innovation Solution
The implementation of at least two field plate gate structures in a semiconductor device, with a small spacing between them to prevent silicide formation, allowing for a more uniform electric field and higher breakdown voltage without the need for a dummy gate structure, thereby enhancing the performance of power MOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate structure is used in high-voltage MOSFETs, then the device can operate at high voltage, but the breakdown voltage cannot be increased further to meet advanced semiconductor fabrication requirements
Solution Approach 1:
The gate structure is divided into multiple segments: a first gate structure, a second gate structure overlapping part of the first gate, and a third gate structure beside the second gate. This segmentation allows each gate to contribute differently to the electric field distribution, enabling increased breakdown voltage while maintaining manageable structural complexity
Solution Approach 2:
The second gate structure is positioned to overlap a portion of the first gate structure in the vertical dimension, while the third gate structure is positioned beside the second gate in the lateral dimension. This multi-dimensional arrangement creates a more uniform electric field distribution throughout the drift region, achieving higher breakdown voltage without excessive complexity
2Object-generated harmful factors
If dummy gate structures are used to prevent silicide formation, then silicide can be blocked, but the device complexity increases
Solution Approach 1:
The silicide-blocking function is extracted from the dummy gate structure and integrated into the functional third gate structure. The third gate structure serves dual purposes: as part of the high-voltage gate system and as the silicide barrier, eliminating the need for separate dummy gates and reducing overall device complexity
Solution Approach 2:
The third gate structure is designed to perform multiple functions simultaneously: it contributes to the electric field distribution for high-voltage operation and acts as a silicide barrier by being positioned close to the second doped region. This multi-functionality eliminates the need for separate dummy gate structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a higher breakdown voltage and improved on-state current in power MOS transistors, allowing for efficient high-voltage operations up to 100 volts or above, while avoiding silicide formation and eliminating the requirement for a dummy gate structure.
Implementation Method 1
The implementation of at least two field plate gate structures in a semiconductor device, with a small spacing between them to prevent silicide formation, allowing for a more uniform electric field and higher breakdown voltage
Data Source
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AI summary
A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A first doped region and a second doped region are formed on the first well doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and adjacent to the first doped region. A second gate structure overlaps the first gate structure and the first well doped region. A third gate structure is formed beside the second gate structure and close to the second doped region. The top surface of the first well doped region between the second gate structure and the third gate structure avoids having any gate structure and silicide formed thereon.