Field Plate PN Junction Layout for Stable Semiconductor Withstand Voltage

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Solution Overview

Problem

Conventional high voltage semiconductor devices face challenges in maintaining reproducible withstand voltage due to variations in impurity concentration and electric field concentration at trench bottom portions, leading to potential breakdown and decreased reliability.

Innovation Solution

The introduction of PN junction diodes at the end portions of field plates in the semiconductor device structure, which mitigates electric field concentration and ensures uniform impurity profiles, thereby stabilizing the withstand voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If impurities are implanted into trench bottom surfaces after trench formation, then N type low concentration regions are formed to promote depletion layer extension and mitigate electric field concentration, but variations in impurity concentrations occur due to implantation dispersion and impurity uptake during heat treatment, leading to poor reproducibility of withstand voltage

Engineering Contradiction:
Improvewithstand voltageVSAvoidimpurity concentration control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming the N type low concentration regions through ion implantation into the drift layer before trench formation, rather than after. This preliminary implantation ensures that the impurity concentration is established before subsequent processing steps (trench etching, field plate formation, heat treatment) that could cause variations. The pre-formed regions maintain their impurity profiles throughout manufacturing, eliminating the reproducibility issues caused by post-trench implantation and heat treatment impurity uptake.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If the basic structure of conventional semiconductor devices is maintained, then manufacturing simplicity is preserved, but electric field concentration at trench bottom portions causes voltage decreases and breakdown

Engineering Contradiction:
Improvestructural simplicityVSAvoidwithstand voltage stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies local quality by introducing N type low concentration regions specifically at the portions of the drift layer that will become the bottom surfaces of trenches, while maintaining the conventional overall device structure. This localized modification creates regions with different impurity concentrations precisely where needed (at future trench bottoms) to mitigate electric field concentration, without altering the basic device architecture or requiring complex manufacturing process changes.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively suppresses voltage decreases at trench bottom portions, enhancing the reproducibility and stability of the semiconductor device's withstand voltage without altering the basic structure of conventional devices.

Implementation Method 1

mitigates electric field concentration

Methodology Applied
Scientific EffectElectric Field: Electric Field

Implementation Method 2

introduction of PN junction diodes at the end portions of field plates

Methodology Applied
Scientific EffectPN junction: Diode

Data Source

PatentUS11764294B2Semiconductor device and semiconductor device manufacturing method
Publication Date: 2023.09.19 LAPIS SEMICON CO LTD
  • US11764294B2 patent drawing
  • US11764294B2 patent drawing
  • US11764294B2 patent drawing

AI summary

A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.