Low Capacitance Field Plate Structure for High Voltage Transistors
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Solution Overview
Problem
Existing field plate structures in transistors, particularly in high power applications, face challenges with high parasitic capacitance and dielectric loading, which affect efficiency under high voltage operations.
Innovation Solution
A Field Effect Transistor (FET) design with a source connected field plate structure featuring a dielectric structure with a thinner intermediate layer acting as an etch stop, allowing for precise etching to create gaps between the field plate and electrode structures, reducing parasitic capacitance and dielectric loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous solid dielectric structure is used to extend from the field plate to the drain, then the field plate structure provides proper electrical isolation and field control, but the parasitic capacitance and dielectric loading increase, reducing efficiency under high voltage operations
Solution Approach 1:
The dielectric structure is segmented into two distinct portions: a first portion with greater thickness extending from the field plate, and a second portion with lesser thickness between the gate and drain. This segmentation allows the dielectric to provide electrical isolation where needed while reducing parasitic capacitance in the high-voltage region between the gate and drain.
Solution Approach 2:
The dielectric structure exhibits local quality variation through its two portions: the first portion has greater thickness for isolation purposes near the field plate, while the second portion has reduced thickness to minimize parasitic capacitance in the critical high-voltage region. This local differentiation optimizes both electrical isolation and capacitance reduction in their respective locations.
2Ease of manufacture
If the field plate structure is connected to the source through a connector section that passes over the semiconductor region, then the manufacturing process is simplified, but the dielectric loading increases due to the continuous dielectric coverage
Solution Approach 1:
The dielectric structure is divided into segments with different thicknesses: a thicker first portion under the field plate connector for manufacturing simplicity, and a thinner second portion in the drain region to reduce dielectric loading. This segmentation maintains ease of manufacture while minimizing energy losses.
3Ease of manufacture
If a uniform thickness dielectric structure is used throughout, then the manufacturing process is simpler and more consistent, but the parasitic capacitance between the gate and drain increases, affecting high voltage performance
Solution Approach 1:
The dielectric structure is segmented into a first portion with greater thickness and a second portion with lesser thickness, allowing simplified manufacturing for the majority of the structure while reducing parasitic capacitance in the critical drain region through the thinner second portion.
Solution Approach 2:
The dielectric structure implements local quality by having uniform thickness in most regions for manufacturing simplicity, while providing a localized thinner second portion in the drain region to reduce parasitic capacitance, thus optimizing both manufacturing and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves lower dielectric loading and reduced parasitic capacitance, resulting in higher efficiency and improved performance under high voltage operations.
Implementation Method 1
A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap
Data Source
AI summary
A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.