Field Plate Design for High Voltage Transistors
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Solution Overview
Problem
High voltage transistor devices face challenges in achieving high breakdown voltages while minimizing switching losses, as existing field plate configurations either burden the gate-to-drain capacitance or require additional processing steps, increasing fabrication costs.
Innovation Solution
A high voltage transistor device with a field plate made from non-gate materials, formed concurrently with the back-end-of-the-line (BEOL) metal layer, which extends from the gate electrode to the drift region, reducing gate-to-drain capacitance and allowing for low-cost fabrication by integrating the field plate within the inter-level dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a field plate is added to high voltage transistor devices to enhance breakdown voltage capability, then breakdown voltage is improved, but gate-to-drain capacitance increases causing higher switching losses
Solution Approach 1:
The field plate is segmented into multiple sections with different conductive materials. The first section uses a first conductive material with higher resistivity, and the second section uses a second conductive material with lower resistivity. This segmentation allows the field plate to simultaneously provide high voltage breakdown capability while controlling capacitance and switching losses.
Solution Approach 2:
Different sections of the field plate have different local properties - the first section has higher resistivity to control capacitance, while the second section has lower resistivity to reduce switching losses. This local quality variation optimizes both breakdown voltage capability and switching performance.
2Reliability
If conventional field plate fabrication methods are used, then field plate functionality is achieved, but additional processing steps increase fabrication costs
Solution Approach 1:
The field plate fabrication is merged with the existing back-end-of-line (BEOL) metal layer processing. The field plate sections are formed using the same deposition and patterning steps as the metal interconnect layers, eliminating additional processing steps and reducing fabrication costs.
Solution Approach 2:
The BEOL metal layer processing serves dual purposes: forming both the field plate structures and the metal interconnect layers. This multi-functionality approach allows the field plate to be integrated without adding separate fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances breakdown voltage capability by manipulating electric fields and reduces switching losses, enabling efficient high-frequency operation while maintaining low fabrication costs.
Implementation Method 1
enhances breakdown voltage capability by manipulating electric fields
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.