Field-Plated Transistor STI Tapering for Lower Peak Electric Fields
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Solution Overview
Problem
Conventional shallow trench isolation (STI) with vertical sidewalls in field effect transistors leads to higher electric fields and degraded device performance, necessitating additional processing for Local Oxidation of Silicon (LOCOS) to enhance field plates, which complicates high circuit density integration.
Innovation Solution
Employing grayscale photolithography to create tapered sidewalls in STI for field-plated transistors, allowing for improved field plate structures without additional mask levels, thereby enhancing transistor performance and reducing peak electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional STI with vertical sidewalls is used, then high circuit density is achieved, but peak electric fields increase and device performance degrades
Solution Approach 1:
The patent applies local quality by creating tapered sidewalls specifically in the STI regions where field plates are located, while maintaining vertical sidewalls in other STI regions. This localized modification reduces peak electric fields at critical locations without altering the overall STI structure, thereby improving device performance while maintaining high circuit density.
Solution Approach 2:
The patent changes the geometric parameter of STI sidewalls from vertical to tapered configuration. This parameter change modifies the electric field distribution, reducing peak electric fields and improving breakdown voltage. The tapered angle can be controlled to optimize the balance between field reduction and device performance.
2Reliability
If LOCOS oxide is added to enhance field plates, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges the field plate enhancement function with the existing STI structure by creating tapered sidewalls in the STI. This eliminates the need for separate LOCOS oxide processing, as the tapered STI itself provides the field reduction effect. The solution combines multiple functions into a single structure, reducing manufacturing complexity while maintaining breakdown voltage improvement.
Solution Approach 2:
The patent extracts the field enhancement function from the separate LOCOS oxide process and integrates it into the STI structure itself. By modifying the STI sidewall geometry, the field plate effect is achieved without requiring additional LOCOS processing steps, thereby simplifying the manufacturing process.
3Ease of manufacture
If STI with vertical sidewalls is used, then manufacturing is simple, but electric field distribution is poor
Solution Approach 1:
The patent introduces dynamic control of the STI sidewall geometry by enabling variable tapered angles through grayscale photolithography. This allows the electric field distribution to be optimized for different device regions while maintaining a single STI formation process. The dynamic adjustment of sidewall angles provides precise control over electric field characteristics without complicating the overall manufacturing flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The tapered sidewalls in STI reduce peak electric fields, improving breakdown voltage and reliability of field-plated transistors while maintaining high circuit density without the need for separate LOCOS oxide.
Implementation Method 1
a grayscale photolithography-based method of forming trench isolation described as being shallow trench isolation (STI) that has at least one tapered sidewall
Data Source
AI summary
An integrated circuit (IC) includes a field-plated transistor including a substrate having a semiconductor surface layer, at least one body region in the semiconductor surface layer, and at least a first trench isolation region adjacent to the body region having at least a first tapered sidewall that has an average angle along its full length of 15 to 70 degrees. A gate is over the body region. A field plate is over the first tapered trench isolation region. A source is on one side of the field plate and a drain is on an opposite side of the field plate. The IC also includes circuitry for realizing at least one circuit function having a plurality of transistors which are configured together with the field-plated transistor that utilize second trench isolation regions for isolation that have an average angle of 75 and 90 degrees.