Field Sequential LCD Pixel Structure Eliminates Color Mixing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Field sequential LCDs face issues with color mixing due to synchronization and timing mismatches between backlight flashing and gate line scanning, leading to color deviation and afterimages, which degrade image quality.

Innovation Solution

The addition of a third and fourth thin film transistor to the pixel structure, along with a frame buffer capacitor, allows for synchronized charging and zero-clearing of the pixel electrode, ensuring optimal timing and voltage distribution, thereby eliminating color mixing and afterimages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If the backlight flashing time is extended to ensure sufficient light output, then the lightness of emergent light is improved, but the color mixing phenomenon is aggravated due to overlap with gate line scanning

Engineering Contradiction:
Improvelightness of emergent lightVSAvoidcolor mixing phenomenon
Core Design Contradiction:
Illumination intensityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the pixel structure into multiple independent components (first TFT, second TFT, third TFT, fourth TFT, frame buffer capacitor, storage capacitor, holding capacitor) that can be independently controlled. This segmentation allows separate control of charging and zero-clearing operations, enabling the backlight to flash continuously while preventing color mixing through coordinated transistor switching.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary charging of the pixel electrode through the first TFT during the vertical blanking period, before the gate line scanning begins. The frame buffer capacitor stores the charged voltage, and the second TFT controls the transfer to the pixel electrode at the appropriate timing, ensuring the pixel is fully charged before backlight flashing starts, thus preventing color mixing while maintaining sufficient light output.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the gate line scanning time is extended to ensure sufficient pixel charging, then the gray scale accuracy is improved, but the backlight flashing time must be reduced, leading to insufficient light output

Engineering Contradiction:
Improvegray scale accuracyVSAvoidlightness of emergent light
Core Design Contradiction:
Manufacturing precisionVSIllumination intensity

Solution Approach 1:

The patent introduces a time dimension separation by using the vertical blanking period (before gate line scanning) for pixel charging through the first TFT, while the gate line scanning period uses the second TFT for voltage transfer from the frame buffer capacitor. This dimensional separation in time allows both sufficient charging time and adequate backlight flashing time to coexist without conflict.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The frame buffer capacitor acts as an intermediary element that decouples the charging process from the display process. It stores the charged voltage from the first TFT during the blanking period and releases it through the second TFT during the scanning period, allowing independent optimization of charging time and backlight flashing time.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the Fb field sequential LCD structure is used to solve color mixing, then the synchronization between backlight and gate line is improved, but the voltage distribution becomes unstable causing afterimages

Engineering Contradiction:
Improvesynchronization between backlight and gate lineVSAvoidvoltage distribution stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies different functional qualities to different parts of the pixel structure: the first TFT and its associated capacitor handle charging with specific voltage characteristics, while the second TFT and frame buffer capacitor handle voltage transfer with different timing characteristics. The third and fourth TFTs provide localized control for zero-clearing operations. This local differentiation ensures stable voltage distribution while maintaining synchronization.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements a feedback mechanism through the third TFT controlled by the zero-clearing signal, which monitors and corrects voltage accumulation in the frame buffer capacitor. When the capacitor voltage exceeds a threshold, the third TFT activates to discharge it, preventing voltage instability and afterimages while maintaining reliable synchronization between backlight flashing and gate line scanning.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration ensures sufficient charging of the pixel electrode and synchronized backlight flashing, eliminating color mixing and afterimages, thereby enhancing image display quality and maintaining a consistent voltage relationship between pixel and output voltages.

Implementation Method 1

the liquid crystal molecules in the upper portion of the screen have already deflected sufficiently

Methodology Applied
Scientific EffectLiquid crystal deflection: Liquid Crystals

Data Source

PatentUS8519930B2Field sequential liquid crystal display device and method
Publication Date: 2013.08.27 SHANGHAI TIANMA MICRO ELECTRONICS CO LTD
  • US8519930B2 patent drawing
  • US8519930B2 patent drawing
  • US8519930B2 patent drawing

AI summary

A field sequential liquid crystal display device includes: first, second, third and fourth thin film transistors, a frame buffer capacitor, a storage capacitor and a holding capacitor connected to the storage capacitor in parallel. The gate of first thin film transistor is connected to a gate line, the source thereof is connected to a data line, the drain thereof is connected to the source of second thin film transistor; the source of second thin film transistor is connected to one end of frame buffer capacitor, the drain thereof is connected to the drain of third thin film transistor; the other end of frame buffer capacitor and a source of third thin film transistor are connected to the drain of fourth thin film transistor, the source of fourth thin film transistor is grounded; and the drain of second thin film transistor is connected to one end of storage capacitor.