Fieldbus I/O Unit Using DMA Buffering for CPU-Free Data Acquisition
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Solution Overview
Problem
Existing input/output units in fieldbus systems require processor-intensive routines for data acquisition and transmission, leading to reduced execution speed due to the use of processor registers for intermediate storage and reliance on timer modules, which are not available for other instructions during data transfer.
Innovation Solution
An input/output unit equipped with a microcontroller featuring an integrated synchronous serial bus interface and a direct memory access (DMA) controller, where data is read at a first clock rate corresponding to the data transmission rate, and then forwarded to a buffer memory, allowing for periodic transfer at a higher clock rate to a fieldbus interface, thereby reducing CPU load and eliminating the need for cumbersome bit shifting routines and timer interrupts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processor registers are used for intermediate storage during data transfer, then data can be transferred from I/O unit to main memory, but the processor is unavailable for other instructions during data transfer, reducing execution speed
Solution Approach 1:
A buffer memory is introduced as an intermediary component between the I/O unit and main memory. Data is first transferred to the buffer memory, which then forwards it to main memory. This mediator allows the processor to continue executing other instructions while data transfer occurs in the background, eliminating the blocking effect on processor execution speed.
Solution Approach 2:
The patent replaces the processor-controlled data transfer mechanism with a direct memory access (DMA) controller. Instead of the processor manually managing data transfer through registers and instructions, the DMA controller autonomously handles the data transfer operation, substituting the mechanical processor control with an automated memory management system that operates independently.
2Manufacturing precision
If timer modules are used to trigger data acquisition and transfer routines, then data can be sampled at required time intervals, but the timer modules are occupied and not available for other instructions
Solution Approach 1:
The buffer memory serves as an intermediary that decouples the sampling operation from the transfer operation. Data can be sampled by the I/O unit and stored in the buffer without requiring timer module intervention for each transfer operation. The buffer management can then proceed independently, freeing timer modules for other timing-critical tasks while maintaining precise sampling intervals.
Solution Approach 2:
The data transfer process is segmented into independent stages: sampling stage (I/O unit to buffer) and transfer stage (buffer to main memory). This segmentation allows different components to handle different stages independently, so timer modules used for sampling control do not need to be occupied during the actual data transfer phase, increasing their availability for other instructions.
3Ease of operation
If bit shifting routines are used to accumulate individual states for packet transmission, then data can be packaged for fieldbus transmission, but the processor load increases and execution speed decreases
Solution Approach 1:
The patent replaces software-based bit shifting routines with hardware-based direct memory access and buffer management. The DMA controller and buffer memory automatically handle the accumulation and packaging of data states into transmission packets, substituting the processor-intensive software routine with an automated hardware mechanism that performs packetization without burdening the processor.
Solution Approach 2:
The buffer memory and DMA controller operate autonomously to perform data packetization. The system serves itself by automatically accumulating individual data states and packaging them for fieldbus transmission without requiring processor intervention. This self-service mechanism eliminates the need for processor-executed bit shifting routines, maintaining packetization capability while preserving processor execution speed.
Data Source
AI summary
An input/output unit for data acquisition in a field bus system includes a microcontroller that has at least one integrated synchronous serial bus interface and a control device for direct memory access. A signal source for a digital signal is connectable to a digital data input master input, slave output (MISO) of the at least one synchronous serial bus interface. The first synchronous serial interface reads in the digital signal present at the data input MISO at a first clock rate that corresponds to a data transmission rate of the at least one synchronous serial bus interface. The control device for direct memory access forwards the read-in data words to a buffer memory, and periodically fetches the read-in data words from the buffer memory and forwards the read-in data words to a second synchronous serial bus interface or to another bus interface.