Fieldbus I/O Data Capture Using DMA and Dual Serial Clocks
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Solution Overview
Problem
Existing input/output units for fieldbus systems require processor-intensive routines for data sampling and transmission, involving cumbersome bit-shifting and timer interrupts, which reduces execution speed and efficiency.
Innovation Solution
An input/output unit with a microcontroller equipped with a synchronous serial bus interface and a direct memory access (DMA) controller, allowing data to be read and processed without CPU-heavy routines, eliminating the need for bit-shifting and timer interrupts by using a first clock rate for data input and a higher clock rate for fieldbus output, enabling efficient data packetization and transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional GPIO sampling with timer interrupts and bit-shifting routines is used, then data can be acquired at required sampling rates, but processor execution speed and efficiency deteriorate due to CPU being unavailable during interrupt handling
Solution Approach 1:
The patent extracts the data acquisition and transmission functions from the CPU by implementing a dedicated I/O unit with its own microcontroller. This separate unit handles GPIO sampling, bit-shifting routines, and fieldbus transmission independently, allowing the main CPU to continue executing other tasks without interruption, thus maintaining both high sampling rates and processor efficiency
Solution Approach 2:
The system is segmented into a main control unit and a separate I/O unit. The I/O unit contains dedicated hardware components for data acquisition including GPIO ports, timer modules, and fieldbus interfaces, separating these functions from the main CPU to enable parallel operation and improve overall system productivity
2Productivity
If processor-intensive routines with timer interrupts are used for data sampling and transmission, then data can be buffered and transmitted cyclically, but device complexity increases due to multiple timer modules and interrupt service routines
Solution Approach 1:
The patent combines multiple functions (GPIO sampling, timing, bit-shifting, buffering, and fieldbus transmission) into a single integrated I/O unit. This consolidation eliminates the need for separate timer modules and interrupt service routines in the main CPU, reducing overall device complexity while maintaining cyclic data transmission capability
Solution Approach 2:
The I/O unit is designed to be self-sufficient with embedded microcontroller that autonomously performs data acquisition, processing, and transmission without requiring external CPU intervention. The unit manages its own timing and buffering operations, eliminating complex interrupt handling and reducing system-wide complexity
3Quantity of substance
If data is read and processed through CPU-heavy routines, then data can be accumulated in buffers, but loss of time occurs due to CPU unavailability during processing
Solution Approach 1:
The patent extracts data processing functions from the CPU by implementing a dedicated I/O unit with embedded microcontroller that autonomously accumulates data in buffers and prepares it for transmission. This eliminates CPU involvement in data accumulation processes, preventing CPU unavailability and time loss while maintaining efficient buffer management
Data Source
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AI summary
The invention relates to an input/output unit, a method and a microcontroller for data capture in a field bus system, the input/output unit comprising a standard microcontroller (11) having an integrated synchronous, serial interface (12) and a control unit (16) for direct memory access. A signal source (17) that generates digital data can be connected at a data input (MISO) of the at least one synchronous, serial interface (12). The first interface (12) reads the data presented at the data input (MISO) at a first clock rate, wherein, for direct memory access, the control unit (16) passes the data words read to a buffer memory (18) and fetches said data words from the buffer memory (18) from time to time and passes said data words to a second synchronous, serial interface (14) or to another bus interface (19). The second interface (14) or the other bus interface (19) is connected to a fieldbus interface (15) and outputs the data words at a higher clock rate than the first clock rate during data capture by the first interface (12).