Shared Memory FIFO Arbiter for Multi-Client Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computing systems, existing technologies face inefficiencies in sharing a single memory resource among multiple devices, leading to dominance issues and inefficiencies in area and power consumption when each device has its own separate memory.
Innovation Solution
A First-In-First-Out (FIFO) system is implemented, where a single shared memory with multiple clients is managed by an arbiter, allowing sequential access to clients through controllers, ensuring each client gets access at least once every N clock cycles, and using virtual or physical partitions to allocate memory space efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each device has its own separate memory, then data access independence is improved, but area and power consumption increase
Solution Approach 1:
The patent merges multiple separate memory resources into a single shared memory resource that serves multiple devices. The shared memory includes multiple storage arrays that can be allocated to different devices, allowing them to share physical memory infrastructure while maintaining logical separation of data. This reduces the total area required compared to providing each device with its own dedicated memory.
Solution Approach 2:
The shared memory is segmented into multiple storage arrays, with each array capable of being allocated to a specific device. This segmentation allows the memory to serve multiple devices independently while using shared physical infrastructure. Each device gets dedicated access to its allocated storage array, maintaining data access independence without requiring separate physical memory modules for each device.
2Area of stationary object
If a single shared memory is used by multiple devices, then area and power consumption are reduced, but access fairness and efficiency deteriorate without proper arbitration
Solution Approach 1:
The patent introduces an arbiter as an intermediary component that manages access to the shared memory among multiple devices. The arbiter receives access requests from multiple devices, determines the appropriate storage array and operation type, and controls the timing of memory access. This intermediary ensures fair and efficient arbitration of memory resources, preventing any single device from dominating the shared memory while maintaining high access efficiency.
3Productivity
If multiple devices access shared memory simultaneously, then resource utilization is improved, but data integrity and access order may be compromised
Solution Approach 1:
The arbiter implements periodic action by granting memory access to different devices in sequential time slots. Instead of allowing truly simultaneous access that would compromise data integrity, the system provides the appearance of concurrent access by rapidly switching between devices in a controlled periodic manner. This ensures that only one device accesses the memory at any given time, maintaining data integrity while achieving high overall resource utilization through efficient time-multiplexed access.
Data Source
AI summary
A First-In-First-Out (FIFO) system and a method for providing access to a memory shared by a plurality of N clients are provided. The memory has a single memory space for holding a plurality of data storage arrays that are respectively configured to store data in a first-in-first-out manner for corresponding clients among the N clients. An arbiter is configured to receive memory access requests from two or more of the N clients to perform a FIFO operation, to push data into a corresponding storage array or to pop data from the corresponding storage array in response to the memory access request. The arbiter is configured to select a first at least one of the clients to perform a first FIFO operation in a first memory operation cycle and to select a second at least one of the clients to perform a second FIFO operation in a second memory operation cycle.


