Video Compression System FIFO Array Segmentation
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Solution Overview
Problem
Conventional video compression systems require a large amount of on-chip resources, leading to stability issues, data loss, and image distortion due to the need for centralized RAMs, which pose challenges in chip layout, wiring, and manufacturing.
Innovation Solution
A video compression system that includes a CPU, a hardware detection module, a write control module, a read control module, and an FIFO array module with a selection switch, which performs hardware detection and reorders functionally normal FIFOs to optimize video compression and improve stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large amount of centralized RAMs are used for video data caching, then video compression function can be implemented, but chip layout complexity and manufacturing risk increase significantly
Solution Approach 1:
The patent divides the centralized RAM structure into multiple independent FIFO modules (Y_FIFOs, U_FIFOs, V_FIFOs). Each FIFO is an independent storage unit that can be managed separately, transforming a monolithic complex structure into modular components that are easier to layout and manufacture while maintaining the required video compression functionality.
Solution Approach 2:
The patent reorganizes the storage architecture from a centralized two-dimensional RAM array into a distributed multi-dimensional FIFO array structure. By distributing Y, U, and V component data across separate FIFO modules with independent address spaces, the system reduces wiring complexity and improves manufacturability while preserving video compression capabilities.
2Quantity of substance
If centralized RAMs with large depth are used, then video data buffering capacity is sufficient, but manufacturing defects cause data inconsistency and image distortion
Solution Approach 1:
The patent segments the buffering capacity across multiple independent FIFO modules instead of using a single large centralized RAM. Each FIFO module has its own read and write pointers and control logic, so that a defect in one FIFO does not affect others. This segmentation maintains total buffering capacity while significantly improving data consistency and reliability.
Solution Approach 2:
The patent implements hardware detection modules that perform preliminary testing of FIFO modules before they are used for actual video compression. The detection mechanism identifies and isolates defective FIFOs in advance, preventing them from causing data inconsistency or image distortion during operation, thus cushioning against potential reliability failures.
3Productivity
If 48 RAMs with depth 16384 are used for BLOCK format conversion, then video compression performance is achieved, but individual problematic RAMs cause project failure
Solution Approach 1:
The patent divides the 48 RAM structure into multiple independent FIFO modules (16 Y_FIFOs, 16 U_FIFOs, 16 V_FIFOs), each with depth 16384. This segmentation allows the system to maintain the required productivity for video compression while improving reliability through modular independence. If one FIFO module fails, the others continue to operate, preventing complete project failure.
Solution Approach 2:
The patent implements hardware detection modules that continuously monitor FIFO module functionality and provide feedback to the control logic. When a defective FIFO is detected, the system receives feedback information and can switch to using only functional FIFOs, thereby maintaining video compression performance while ensuring project stability through active reliability management.
Data Source
AI summary
Disclosed in the present disclosure are a video compression system and a server. The video compression system includes a Central Processing Unit (CPU), a hardware detection module, a write control module, a read control module, and an First In First Out (FIFO) array module; the CPU is configured to send a first enable signal to the hardware detection module, the read control module, and the selection switch; the selection switch is configured to select to write test data into the FIFO array module through the hardware detection module based on the first enable signal; the hardware detection module is configured to write test data into the FIFO array module based on the first enable signal; and the read control module is configured to read the test data from the FIFO array module based on the first enable signal and transmit the test data to the hardware detection module.