Semiconductor Memory FIFO Buffer Address Matching for Power Reduction
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Solution Overview
Problem
Semiconductor memory devices associated with graphic data face high power consumption and noise due to high-frequency clock signals, leading to increased power consumption and noise when data is read from a memory cell array.
Innovation Solution
Incorporating a data first-in/first-out (FIFO) circuit that stores and outputs data from a memory cell array, reducing the need to constantly read from the memory cell array by matching current addresses with previous addresses, thereby minimizing current consumption during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If data is continuously read from the memory cell array during high-frequency clock operations, then data output is maintained, but power consumption and noise increase
Solution Approach 1:
The patent implements a FIFO circuit that pre-stores read data from the memory cell array before it is needed for output. By anticipating future read requests and preparing data in advance, the system can serve output requests from the FIFO buffer without continuously accessing the memory cell array, thereby reducing power consumption while maintaining data output capability.
Solution Approach 2:
The FIFO circuit acts as an intermediary buffer between the memory cell array and the output interface. It decouples the high-frequency read operations from the memory cell array by storing data temporarily, allowing the memory array to be accessed less frequently while the FIFO handles the continuous data output requirement.
2Reliability
If the same data is re-read from the memory cell array, then data accuracy is maintained, but current consumption increases
Solution Approach 1:
The address comparing circuit implements a feedback mechanism by monitoring read addresses and comparing them with previously accessed addresses. When a match is detected, the system recognizes that the same data is being requested again and retrieves it from the FIFO buffer instead of re-reading from the memory cell array, thus maintaining data accuracy while reducing current consumption.
Solution Approach 2:
The system creates a copy of read data in the FIFO buffer, which can then be served multiple times without accessing the original memory cell array. This copying mechanism allows the same data to be reused for multiple output requests, reducing the need for repeated reads from the memory array.
3Speed
If high-frequency clock signals are used for graphic data operations, then processing speed is improved, but noise increases
Solution Approach 1:
The patent reduces the frequency of memory cell array access operations by using periodic batching through the FIFO buffer. Instead of continuous high-frequency reads, the system performs memory accesses at lower frequency intervals, allowing the FIFO to handle data staging and reducing noise-generating high-frequency operations while maintaining overall processing speed.
Data Source
AI summary
A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.