Deterministic FIFO Buffer Latency Tuning via Counter Bit Extension
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Solution Overview
Problem
Existing FIFO buffers in data communication circuits lack accurate methods for determining latency, leading to inefficiencies in occupancy measurement and latency adjustment, particularly in applications requiring precise synchronization and low latency.
Innovation Solution
The implementation of a FIFO buffer circuit with write and read counters of length one bit longer than necessary, utilizing exclusive-or logic to generate pulse signals for occupancy determination, and phase-locked loop for precise phase variation to measure duty cycles, allowing for accurate latency tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If FIFO buffers use conventional occupancy measurement methods, then the buffer can operate, but latency determination is inaccurate and synchronization precision deteriorates
Solution Approach 1:
The patent segments the occupancy measurement process into distinct phases: writing phase (when write pointer advances) and reading phase (when read pointer advances). By separating these measurements and using phase-locked loops to synchronize with respective clock domains, the system achieves accurate latency determination for each phase independently, resolving the contradiction between measurement precision and synchronization reliability.
Solution Approach 2:
The patent performs preliminary actions by pre-configuring the measurement system with write and read counters, phase-locked loops, and duty cycle measurement logic before actual FIFO operation. The system pre-establishes the measurement framework that enables accurate latency determination without disrupting normal FIFO buffer operation, thereby maintaining both precision and reliability.
2Stability of the object's composition
If FIFO buffers increase depth to reduce latency variations, then latency stability improves, but total delay increases and productivity deteriorates
Solution Approach 1:
The patent implements feedback by continuously measuring the actual occupancy level through duty cycle analysis and using this information to dynamically adjust the FIFO depth configuration. The system monitors latency variations in real-time and provides feedback to optimize buffer size, achieving latency stability without requiring excessive buffer depth that would reduce throughput efficiency.
Solution Approach 2:
The patent changes the parameter of FIFO depth from a fixed conventional value to a dynamically optimized value based on measured occupancy patterns. By analyzing duty cycles and occupancy levels, the system determines the minimum necessary buffer depth to achieve desired latency stability, thereby avoiding the productivity loss associated with oversized buffers while maintaining composition stability.
3Device complexity
If FIFO buffers use minimal counter bits to address the buffer, then device complexity is reduced, but latency measurement accuracy deteriorates
Solution Approach 1:
The patent introduces intermediary elements (phase-locked loops and duty cycle measurement logic) that enable accurate occupancy measurement without requiring increased counter bit length. The PLI acts as a mediator that translates the limited counter information into precise occupancy levels through phase comparison and duty cycle analysis, resolving the contradiction between device complexity and measurement precision.
Data Source
AI summary
One embodiment relates to a method for determining a latency of a FIFO buffer. A highest-order bit is provided from FIFO write and read counters to input-comparison logic that distinguishes between the highest-order write and read bits having a same logic level and the highest-order write and read bits having different logic levels. The occupancy level, and hence the latency, of the FIFO buffer is determined based on the output of the input-comparison logic. Another embodiment relates to a FIFO buffer having write and read counters that each have a length in bits that is one bit longer than is needed to address the FIFO buffer. Another embodiment relates to a method of tuning a latency of a FIFO buffer. Other embodiments and features are also disclosed.