FIFO Buffer Data Transfer for Neural Network Simulator Speed
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Solution Overview
Problem
Conventional instruction set simulators are limited by hardware bus bandwidth, leading to slow data processing speeds when simulating large computation processors like neural network processors, which hinders quick verification of hardware functions.
Innovation Solution
A data processing method and device that utilizes FIFO memories to transfer and process image and weight data in large granularities, performing convolution operations when sufficient data is cached, thereby bypassing hardware bus bandwidth limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional instruction set simulator processes data according to hardware bus bandwidth limitations, then hardware function simulation accuracy is maintained, but data processing speed becomes very slow
Solution Approach 1:
The patent pre-transfers N input image data and M weight data into FIFO buffers before convolution operations are needed. This preliminary data preparation allows the convolution unit to perform operations immediately when data is ready, without being constrained by hardware bus bandwidth during the actual computation, thereby significantly improving data processing speed and verification efficiency
Solution Approach 2:
The patent introduces FIFO buffers as intermediary storage components between the memory system and the convolution unit. These FIFO buffers decouple the data transfer rate from the computation rate, allowing the system to process data faster than the hardware bus would normally permit by buffering data in advance and enabling continuous high-speed convolution operations
2Quantity of substance
If image data size is 4096 bits and hardware bus bandwidth is 256 bits, then data must be processed in 16 separate transfers, but this increases processing time and reduces simulation efficiency
Solution Approach 1:
The patent segments the large 4096-bit image data into smaller 256-bit chunks that match the hardware bus bandwidth, transferring them in batches of N=16 simultaneously into the FIFO buffer. This segmentation allows the system to fully utilize the hardware bus bandwidth while maintaining the ability to process the complete large dataset without repeated slow transfers
Solution Approach 2:
The patent merges multiple small data transfers (N input image data batches and M weight data batches) into a single coordinated operation that fills the FIFO buffers. By combining these transfers and processing them together through the convolution unit, the system eliminates the need for sequential processing of 16 separate 256-bit transfers, thereby reducing total processing time while maintaining data integrity
Data Source
AI summary
A data processing method comprises: if detecting that a number of image data to be transferred is greater than zero wherein the number of image data is a product of a number of input image data and a number of output image data, and a first available storage space of a FIFO memory is greater than or equal to a storage space occupied by an N number of input image data, transferring the N input image data in a first memory to the first FIFO memory; if detecting that a number of weight data to be transferred is greater than zero wherein the number of weight data is a product of the number of input image data and the number of output image data, and a second available storage space of a second FIFO memory is greater than or equal to a storage space occupied by an M number of weight data, transferring the M weight data in a second memory to the second FIFO memory; when the number of input image data cached in the first FIFO memory and the number of weight data cached in the second FIFO memory are greater than or equal to 1, performing a convolution operation on input image data i read from the first FIFO memory and weight data w read from the second FIFO memory to obtain output image data corresponding to an output index of the weight data w, wherein N, M, i, and w are integers.