FIFO Buffer for Non-Aligned System Bus Data Transfer
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Solution Overview
Problem
Current system bus data transfer methods require data to be an integer multiple of the bus width, leading to increased transfer time and processing power when data is not aligned, and prevent access to non-aligned system bus addresses.
Innovation Solution
A method and apparatus utilizing a FIFO buffer with a width wider than the system bus, supported by a high-speed AMBA bus, allowing non-integer multiple data transfers and enabling data alignment at non-aligned addresses through a transfer algorithm that calculates the buffer width and includes an extra bit for tracking bytes, facilitating efficient data transfer between devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is padded to an integer multiple of system bus width, then data transfer can proceed, but transfer time increases and processing power is consumed
Solution Approach 1:
The patent segments the data transfer process into multiple smaller transfers. Instead of padding a single large data block to the next integer multiple of bus width, the data is divided into chunks that can be transferred individually. Each chunk is transferred without requiring padding to a full bus width multiple, thereby reducing the total padding overhead and improving transfer efficiency while minimizing time loss.
Solution Approach 2:
The patent employs partial action by transferring only the necessary portion of data in each bus transaction rather than always filling the entire bus width. This allows the system to transfer variable-length data packets efficiently without wasting bus cycles on padding bits, thus improving productivity while reducing the time penalty associated with excessive padding.
2Productivity
If data is padded to an integer multiple of system bus width, then transfer can occur, but additional processing power is required
Solution Approach 1:
By segmenting data into smaller transfer units, the patent reduces the computational overhead required for padding operations. Instead of processing large blocks of data that require extensive padding calculations and memory operations, the segmented approach allows for more granular and efficient processing, reducing the energy consumption associated with data preparation and transfer operations.
Solution Approach 2:
The patent changes the parameter of data transfer size to match actual data requirements rather than fixed bus width multiples. This dynamic adjustment of transfer parameters eliminates unnecessary padding operations, thereby reducing the processing power and energy consumption required for data preparation while maintaining full data transfer capability.
3Ease of operation
If system bus requires aligned addresses, then simple addressing is used, but access to non-aligned addresses is prevented
Solution Approach 1:
The patent introduces dynamic addressing capabilities that allow the system to adapt between aligned and non-aligned address access. The addressing mechanism can dynamically adjust to handle both simple aligned addresses and complex non-aligned addresses, providing versatility while maintaining operational ease for common cases. This dynamic approach enables the system to access any memory address without being constrained by alignment requirements.
Solution Approach 2:
The patent creates a universal addressing system that can handle both aligned and non-aligned addresses through a single unified mechanism. This multi-functional addressing approach eliminates the need for separate handling paths for different address types, thereby maintaining simplicity while expanding adaptability to cover the entire address space including non-aligned addresses.
Data Source
AI summary
Disclosed are a method and apparatus of non-system bus width data transfer executable at a non-aligned system bus address. In one embodiment, a method of a controller is described. The method includes applying a FIFO buffer having a buffer width (e.g., determined using a transfer algorithm) that is wider than that of a system bus width. A system bus that permits transfer of data amounts which are non-integer multiples of a width of the system bus is used. The system bus is designed such that it supports any non-aligned system bus address. Data is transferred between devices coupled to the system bus.