Asynchronous FIFO Buffer for Redundant Memory Columns
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Solution Overview
Problem
In memory devices, the presence of defective NAND strings can lead to inefficiencies in data access and storage, as existing solutions often require discarding entire blocks due to a few defective columns, and the access circuitry for primary and redundant columns have different parallelism levels, affecting data transfer rates.
Innovation Solution
The implementation of first-in, first-out (FIFO) buffers acts as an interface between the controller and the latches of redundant columns, allowing data to be exchanged at a higher clock rate with the controller while maintaining a slower clock rate with the latches, enabling asynchronous data transmission and prefetching of read data to replace defective primary columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FIFO buffers are introduced to enable asynchronous data transmission between controller and redundant columns, then data transfer rate with controller is improved, but device complexity increases
Solution Approach 1:
FIFO buffers are introduced as intermediary components between the controller and the latches of redundant columns. These buffers enable asynchronous data transmission by decoupling the data paths, allowing the controller to operate at a higher clock rate while the latches operate at a slower clock rate. The FIFO buffers absorb the timing differences and coordinate data flow between the two different clock domains, thereby resolving the contradiction between improving data transfer rate and maintaining device complexity.
2Reliability
If redundant columns are added to replace defective primary columns, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by providing FIFO buffers specifically for redundant columns rather than uniformly across all columns. The access circuitry for redundant columns is differentiated from primary columns, with dedicated FIFO buffers only where needed for asynchronous data exchange. This localized approach allows reliability improvement through redundant column support without proportionally increasing overall device complexity.
3Speed
If different parallelism levels are used for primary and redundant columns access circuitry, then data transfer rate for primary columns is improved, but ease of operation deteriorates
Solution Approach 1:
The access circuitry is segmented into different paths for primary columns and redundant columns. Primary columns utilize high-parallelism access circuitry optimized for speed, while redundant columns utilize asynchronous access circuitry with FIFO buffers. This segmentation allows each column type to have optimized access characteristics, with the controller managing both paths through coordinated control signals, thereby maintaining ease of operation despite different parallelism levels.
Data Source
AI summary
Apparatuses and techniques are described for accessing redundant columns of data in a memory device. To facilitate scaling of a memory device and reduce a clock rate used to access latches of the redundant columns in program and read operations, one or more first-in, first out (FIFO) buffers are provided to output data to, and receive data from, the latches. The FIFO buffers act as an interface between a controller and the latches, and exchange data with the controller at a relatively high clock rate, and exchange data with the latches of the redundant columns at a slower clock rate. During a read operation, the FIFO can prefetch read data from one or more columns and store it until it is needed to replace the data of a defective primary column.