FIFO Buffer Re-timing with Loop-Filtered Clock Control

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Solution Overview

Problem

Existing systems that process sampled data, such as video and audio streams, face challenges in maintaining a stable sample rate when routing data between different sources and destinations, particularly in packet-based systems where data is delivered at varying rates, requiring a method to adapt quickly to changing average input sample rates.

Innovation Solution

The method involves storing input data samples in a FIFO buffer and controlling the output clock frequency using a loop-filtered measure of the buffer fill level, combined with an estimate of the input data rate, and employing a variable recursive filter to adjust the filter characteristic based on the buffer fill level, ensuring minimal short- and medium-term jitter in the output sample rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a time-division multiplex operates at a rate not precisely coupled to the required sample rate, then routing flexibility between different data sources and destinations is improved, but the sample rate stability and jitter performance deteriorate

Engineering Contradiction:
Improverouting flexibilityVSAvoidsample rate stability
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent introduces a re-timing device as an intermediary component between the time-division multiplex and the data destination. This device includes a FIFO buffer and control logic that mediates the rate mismatch by buffering samples and controlling their output timing based on loop-filtered feedback from the buffer fill level, thereby maintaining sample rate stability while allowing routing flexibility

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a feedback control mechanism where the output clock frequency is adjusted based on loop-filtered feedback from the FIFO buffer fill level. The system continuously monitors the buffer fill level, filters this signal through a loop filter, and uses it to control the output clock frequency, creating a closed-loop system that maintains stable sample rate despite variations in input rate

Inventive Principle:
Principle #23Feedback

2Device complexity

If the re-timing method uses a fixed filter characteristic, then the system is simpler to implement, but the adaptation speed to changing average input sample rates deteriorates

Engineering Contradiction:
Improvefilter characteristicVSAvoidadaptation speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent makes the filter characteristic dynamic by varying it based on the loop-filtered measure of the FIFO buffer fill level. When the buffer fill level indicates a need for faster adaptation, the filter characteristic is adjusted to allow quicker response, while under normal conditions the filter provides smoother control. This dynamic adjustment enables the system to adapt quickly to changing input rates while maintaining stability during normal operation

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9397774B2Re-timing sampled data
Publication Date: 2016.07.19 GRASS VALLEY LTD
  • US9397774B2 patent drawing
  • US9397774B2 patent drawing

AI summary

For re-timing sampled data, input data samples at an input data rate are stored in a FIFO buffer and output at an output data rate according to an output clock that is locked to the input data rate in dependence on a loop-filtered measure of the fill level of the said buffer. The frequency of the output clock is additionally controlled by an estimate of the input data rate.