FIFO Buffer Write Control via Decoupled Shift Scheduling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
FIFO buffer structures face timing performance misalignments due to high fanout values and capacitive loads, leading to degradation in signal transition times, especially in designs with multiple memory locations and large sizes, which complicates the control of write operations and shifts.
Innovation Solution
The solution involves a fast-write FIFO micro-architecture that decouples write and shift operations by scheduling shifts in the next clock cycle, eliminating the need for immediate shift operations during write operations, and using a finite-state machine to manage the write location and buffer networks independently, reducing the impact of fanout on timing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If write operations drive multiple memory locations with high fanout, then data can be written to any location, but timing performance degrades due to capacitive loads
Solution Approach 1:
The patent segments the write operation into two independent parts: (1) writing data to a single designated write location, and (2) shifting data between locations. This segmentation eliminates the need for the write enable signal to drive all memory locations simultaneously, reducing fanout from N locations to just 1 write location plus the shift register chain.
Solution Approach 2:
The patent performs the shift operation in advance or in parallel with the write operation by using a separate shift control signal that operates independently. The shift register is configured to shift data to the next location before or during the write cycle, so that when data needs to be written to a specific location, it is already positioned there through the shift operation.
2Reliability
If buffer cells are added to reduce fanout violations, then timing violations are prevented, but implementation delay increases
Solution Approach 1:
The patent extracts the shift function from the write operation and implements it as a separate, dedicated shift register with its own control signal. This extraction allows the write enable signal to have minimal fanout (only to the write location and write control logic) while the shift function handles data movement to other locations independently, eliminating the need for extensive buffer cell networks.
Solution Approach 2:
The shift register acts as an intermediary between the write location and other memory locations. Instead of the write enable signal directly controlling all locations, the shift register mediates data movement, receiving data from the write location and automatically shifting it to subsequent locations, thereby reducing the control signal fanout while maintaining data integrity.
3Ease of operation
If write enable signal drives all locations and multiplexers, then write operation is controlled, but fanout becomes excessively high
Solution Approach 1:
The patent introduces dynamic control through separate write enable and shift enable signals that are activated at different times or under different conditions. The write enable signal is active only during the write cycle to control the write location, while the shift enable signal is active during shift cycles to control data movement. This dynamic separation reduces the instantaneous fanout of any single control signal.
Solution Approach 2:
The patent applies local quality by giving different control signals different scopes of influence: the write enable signal has local scope (affecting only the write location and immediate write control logic), while the shift enable signal has extended scope (affecting the shift register chain). This localized control approach minimizes the fanout of critical write control signals while maintaining overall write operation control.
Data Source
AI summary
The operation of a FIFO buffer memory includes writing the data at input to the memory in a single write location, and making the single write location available for writing an input datum with a shift of the datum written in the single write location to another location of the memory. At each operation of writing of an input datum in the single write location, there is scheduled shifting of the datum written therein to another location, without waiting for a new write request, thus eliminating the combinational constraint between the two operations.