FIFO Circuit Design for 3D Memory Power and Area Reduction
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Solution Overview
Problem
High power consumption and increased layout area in 3D memory devices, such as Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM), due to the need for multiple flip-flop or latch circuits to maintain data order and perform data bus inversion (DBI) operations, which complicates data transmission and increases energy usage.
Innovation Solution
A FIFO circuit design that incorporates a series and parallel configuration of latch circuits with NAND circuits, utilizing pointer signals to manage data flow efficiently, allowing for longer data storage periods with reduced power consumption and layout area by optimizing the number of clock cycles required for data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple flip-flop or latch circuits are used to maintain data order and perform DBI operations, then data reliability and transmission order are improved, but power consumption and layout area increase
Solution Approach 1:
The patent combines the data storage function and DBI operation function into a single integrated FIFO circuit structure. The latch circuits perform both data buffering and DBI calculation functions simultaneously, eliminating the need for separate circuits and reducing overall power consumption while maintaining data reliability.
Solution Approach 2:
The FIFO circuit is designed to perform multiple functions: data buffering, order maintenance, and DBI operation execution. This multi-functional design reduces the total number of circuits needed, thereby reducing power consumption and layout area while preserving data reliability.
2Reliability
If multiple flip-flop or latch circuits are used to maintain data order and perform DBI operations, then data transmission order is improved, but layout area increases
Solution Approach 1:
The patent merges data storage and DBI operation circuits into a single integrated structure. The same latch circuits that store data also perform DBI calculations, significantly reducing the layout area required while maintaining data transmission order through the sequential nature of the FIFO structure.
Solution Approach 2:
The patent utilizes the time dimension through clocked operation of latch circuits to achieve data ordering without requiring additional spatial resources. By using sequential clock cycles to control data flow and DBI operations, the design reduces spatial complexity while maintaining transmission order.
3Reliability
If traditional FIFO circuit designs are used, then data integrity is maintained, but power consumption and area are higher
Solution Approach 1:
The patent integrates DBI operation circuits within the FIFO structure, combining data buffering and data inversion operations into a single unified circuit. This reduces overall circuit complexity while maintaining data integrity through the coordinated operation of shared resources.
4Duration of action of moving object
If more latch circuits are used to extend data storage period, then data storage duration is improved, but power consumption and area increase
Solution Approach 1:
The patent uses periodic clock signals to control the latch circuits, enabling data to be held for extended periods without requiring additional circuits. The clocked latch structure allows data to be retained through multiple clock cycles while consuming minimal power, as latches only consume significant power during state transitions.
Data Source
AI summary
Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.