FIFO Clock Alignment for Low-Skew High-Speed Serial Lanes
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Solution Overview
Problem
High-speed serial interfaces, such as JESD204B, face challenges in maintaining low latency variation across parallel data lanes due to asynchronous read and write clocks in FIFO buffers, leading to potential skew issues that exceed industry specifications.
Innovation Solution
An alignment circuit system that generates control signals to synchronize read and write clocks, using a phase-locked loop (PLL) to ensure consistent reset signals and manage buffers with locally-generated clocks having rational frequency ratios, thereby minimizing latency variation across parallel lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous read and write clocks are used in FIFO buffers to handle different data rates, then the buffer can accommodate flexible data transfer ratios, but latency variation increases and exceeds skew allowances
Solution Approach 1:
The patent divides the single FIFO buffer into multiple parallel FIFO buffers, each handling a portion of the data stream. By segmenting the data path and using multiple buffers with aligned clocks, the system maintains flexibility in data transfer ratios while reducing latency variation within each segment, thereby resolving the contradiction between adaptability and precision.
Solution Approach 2:
The patent introduces an alignment circuit as an intermediary component that synchronizes the read and write clocks of the FIFO buffers. This mediator ensures that despite the asynchronous nature of the data rates, the actual clock operations are aligned, thereby maintaining low latency variation while still accommodating flexible transfer ratios.
2Productivity
If FIFO buffers are used to transfer bitstream between clock domains, then data rate matching is achieved, but latency inconsistency occurs due to asynchronous clocks
Solution Approach 1:
The data stream is segmented into multiple parallel paths, each with its own FIFO buffer. This segmentation allows each buffer to handle data at matched rates while the overall system maintains latency consistency through the alignment of clock domains across the segmented paths.
Solution Approach 2:
The alignment circuit implements a feedback mechanism that monitors the phase relationship between read and write clocks and adjusts the clock timing accordingly. This feedback ensures that data rate matching is achieved while maintaining consistent latency across all FIFO buffers.
3Device complexity
If power of 2 serialization ratios are used in high-speed analog circuits, then circuit complexity is reduced and speed is improved, but latency variation increases due to asynchronous clock domains
Solution Approach 1:
The serialization process is segmented into multiple parallel channels, each operating at power of 2 ratios. This segmentation allows each analog circuit to maintain simplicity and high speed while the collective system achieves low latency variation through the parallel structure and clock alignment.
Solution Approach 2:
Multiple parallel serialization channels are merged into a unified output stream. By combining the outputs of multiple simple, fast power-of-2 serializers with aligned clocks, the system achieves both low complexity and low latency variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system achieves low latency variation of approximately 0.2 write clock periods, ensuring consistent latency across all lanes and aligning read and write clocks, thus adhering to industry skew allowances.
Implementation Method 1
using a phase-locked loop (PLL) to ensure consistent reset signals and manage buffers with locally-generated clocks
Data Source
AI summary
A device that supports communication over parallel serial lanes may include an analog circuit domain, a digital circuit domain, a buffer between the analog domain and the digital domain, and an alignment circuit. The buffer may receive data from the digital domain according to a write clock and send out the received data to the analog domain according to a read clock. The alignment circuit may generate control signals to initiate reading from the buffer when the read clock and write clocks are aligned. In one embodiment, the device may be an analog-to-digital converter (ADC) integrated circuit (IC) chip and the buffer may be a FIFO.