Clock Phase Adjustment for Low-Latency FIFO Buffers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The random phase relationship between receiver recovered clock (RRCLK) and core logic clock (CCLK) at clock-domain boundaries increases latency in FIFO buffers, degrading performance in serializer/deserializer circuits.
Innovation Solution
A clock-adjustment circuit comprising a phase-detection circuit and a phase-adjustment circuit that determines and adjusts the phase of RRCLK relative to CCLK to a deterministic phase relationship, avoiding the metastable range of the FIFO buffer, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FIFO buffer is used to transfer data between RRCLK and CCLK clock domains with random phase relationship, then data transfer between clock domains is enabled, but latency is significantly increased due to the need for guard band stages
Solution Approach 1:
The patent changes the phase parameter of the RRCLK clock relative to CCLK from a random relationship to a fixed deterministic relationship. By adjusting the phase of RRCLK to be deterministic relative to CCLK, the system eliminates the need for guard band stages in the FIFO buffer, thereby reducing latency while maintaining data transfer reliability between clock domains.
2Adaptability or versatility
If the phase of RRCLK is kept random to follow sampled data, then clock-data recovery flexibility is maintained, but the phase relationship with CCLK becomes unpredictable causing increased FIFO latency
Solution Approach 1:
The patent applies preliminary action by adjusting the phase of RRCLK in advance before data transfer operations. The phase-adjustment circuit pre-establishes a deterministic phase relationship between RRCLK and CCLK, ensuring that subsequent FIFO operations can proceed with minimal latency. This preliminary phase alignment prevents the need for additional guard band stages during actual data transfer.
3Reliability
If guard band stages are added to FIFO buffer to handle random phase variations, then metastability is avoided, but latency is increased
Solution Approach 1:
The patent extracts and removes the need for guard band stages from the FIFO buffer design. By establishing a deterministic phase relationship between RRCLK and CCLK through the phase-adjustment circuit, the system eliminates the requirement for additional guard band stages that would otherwise be needed to handle random phase variations. This extraction of the guard band requirement directly reduces FIFO latency while maintaining metastability avoidance.
Data Source
AI summary
In a clock-adjustment circuit, a phase-detection circuit receives a first clock associated with a first clock domain and a second clock associated with a second clock domain, and determines a phase relationship between the first clock and the second clock. Then, the phase-adjustment circuit in the clock-adjustment circuit adjusts a phase of the first clock relative to the second clock if the determined phase relationship is associated with a metastable range of a first-in first-out (FIFO) buffer that transfers data from the first clock domain to the second clock domain, thereby reducing latency associated with the FIFO buffer.