FIFO-Based Clock Control for Low-Power Digital Circuits

Solution Overview

Problem

Semiconductor devices consume excessive power due to high clock frequencies, leading to increased heat generation and potential failure, as they often require high clock speeds to meet system requirements.

Innovation Solution

Implementing a mechanism to dynamically control clock frequency based on the workload of the digital circuit, adjusting it according to the amount of data in a FIFO buffer to reduce power consumption by eliminating redundant CPU cycles and idling pipeline stages when not in use.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high clock frequency is used to meet system requirements, then processing speed is improved, but power consumption increases

Engineering Contradiction:

Improveprocessing speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the clock frequency adjustable rather than fixed. The clock control circuit dynamically changes the clock frequency based on the workload detected from FIFO buffer status, allowing the system to adapt between high performance and low power consumption states as needed

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the clock frequency parameter based on system conditions. By monitoring the FIFO buffer and adjusting the clock frequency accordingly, the system optimizes the balance between processing speed and power consumption, using higher frequencies only when data processing is required

Inventive Principle:

Principle #35Parameter changes

2Speed

If high clock frequency is used, then processing speed is improved, but heat generation increases

Engineering Contradiction:

Improveprocessing speedVSAvoidheat generation

Core Design Contradiction:

SpeedVSTemperature

Solution Approach 1:

The patent implements periodic action by using burst-mode processing. The clock is activated periodically based on data availability in the FIFO buffer, creating intervals of high-speed processing followed by low-power idle states, thereby reducing average heat generation while maintaining processing capability

Inventive Principle:

Principle #19Periodic action

3Speed

If high clock frequency is used, then processing speed is improved, but device reliability decreases

Engineering Contradiction:

Improveprocessing speedVSAvoiddevice reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies dynamics by making the clock frequency adjustable rather than fixed. The clock control circuit dynamically changes the clock frequency based on the workload detected from FIFO buffer status, allowing the system to adapt between high performance and low power consumption states as needed

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the clock frequency parameter based on system conditions. By monitoring the FIFO buffer and adjusting the clock frequency accordingly, the system optimizes the balance between processing speed and power consumption, using higher frequencies only when data processing is required

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9035678B2Method and apparatus for reducing power consumption in a digital circuit by controlling the clock

Publication Date: 2015.05.19 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.