Multi-Register FIFO Clock Restart Synchronization
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Solution Overview
Problem
In digital circuits with multiple clock domains, synchronization issues arise when the source clock signal is temporarily switched to a power-off status, causing the first clock signal to restart before the second clock signal, leading to erroneous counting values due to the second clock signal remaining at a fixed voltage level, preventing components from sampling the reset signal properly.
Innovation Solution
A FIFO apparatus with multiple write registers, a first control circuit, a multiplexer, and a second control circuit is used to generate and manage toggling pulses, ensuring that the write registers are enabled according to a sequence, and the multiplexer outputs signals based on the difference in delay times between the first and second clock signals, with the number of write registers being equal to or larger than the cycle difference, thereby maintaining data integrity across clock domain transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the source clock signal is switched to power-off status for power saving, then energy consumption is reduced, but the first clock signal restarts before the second clock signal causing synchronization errors
Solution Approach 1:
The patent applies preliminary action by using a first toggling pulse generated in advance (before the second clock signal restarts) to preemptively reset the second counter. This ensures that when the second clock signal resumes, the counter is already in the correct state, preventing synchronization errors while allowing the clock to be powered off for energy saving.
Solution Approach 2:
The patent introduces a first toggling pulse as an intermediary signal that mediates between the first clock domain and the second clock domain. This toggling pulse serves as a bridge to transfer the reset state from the first counter (which restarts first) to the second counter, ensuring synchronization without requiring both clocks to restart simultaneously.
2Loss of energy
If the second clock signal remains at fixed voltage level during restart, then power consumption is reduced, but components cannot sample the reset signal properly causing counter overflow
Solution Approach 1:
The reset action is performed in advance while the first clock signal is still active and can generate the first toggling pulse. This preliminary reset ensures that when the second clock signal later resumes from its fixed voltage state, the counter is already reset and ready to operate correctly, eliminating the need for the second clock to be actively sampling during the reset phase.
3Reliability
If the number of write registers is increased to cover the delay difference, then data integrity is maintained, but device complexity increases
Solution Approach 1:
The patent changes the parameter of using a toggling pulse signal instead of relying on a large number of write registers to cover the delay difference. By transforming the approach from spatial redundancy (more registers) to temporal control (toggling pulse timing), the solution maintains data integrity while reducing device complexity.
Data Source
AI summary
A FIFO apparatus includes write registers, a first control circuit, a multiplexer, and a second control circuit. The write registers are for receiving an input signal and the first clock signal, and outputting first outputs to a multiplexer. The first control circuit is for receiving a first clock signal, generating a first toggling pulse, and enabling the write registers according to a sequence. The second control circuit is for controlling the multiplexer according to the first toggling pulse and a second clock. The multiplexer outputs a second output according to the sequence. The first and second clock signals have a first delay time and a second delay time, respectively. Difference between the first and second delay times is equal to M cycle(s) of the first clock signal, and a number of the write registers is equal to or larger than M.