Clock Domain Crossing Timestamping via FIFO Averaging

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Solution Overview

Problem

Systems that transfer data packets between different clock domains face challenges in synchronizing timing information accurately, particularly due to independent clock operations and potential time jitter, which affects the reliability of time stamps in data transmission.

Innovation Solution

An apparatus comprising a buffer, a processor, and a FIFO (First-In-First-Out) memory structure that updates and derives a point in time by averaging or weighting multiple clock values, compensating for clock frequency deviations and abrupt shifts, ensuring accurate time stamping across clock boundaries.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data packets are transferred between independent clock domains, then data transmission capability is improved, but time synchronization accuracy deteriorates due to clock boundary and time jitter

Engineering Contradiction:
Improvedata transmission capabilityVSAvoidtime synchronization accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The system divides the time stamping function into two independent parts: a first time stamp generator operating in the first clock domain that captures the time value, and a second time stamp generator operating in the second clock domain that processes the time value. This segmentation allows each generator to operate independently in its own clock domain without interference, thereby maintaining time synchronization accuracy while enabling data transmission between clock domains.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A buffer is introduced as an intermediary element between the two clock domains. The buffer stores the time value generated in the first clock domain and makes it available to the second time stamp generator in the second clock domain. This intermediary mechanism resolves the clock boundary issue by providing a stable interface between independent clock domains, preventing time jitter from affecting synchronization accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If a single clock domain is used for time stamping, then time synchronization accuracy is improved, but adaptability to different clock domains deteriorates

Engineering Contradiction:
Improvetime synchronization accuracyVSAvoidadaptability to different clock domains
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The time stamping apparatus is designed with dual functionality: it can operate within a single clock domain or across multiple independent clock domains. The first and second time stamp generators are both capable of generating time stamps, and the buffer can operate in different modes (single-clock or multi-clock). This universal design allows the system to adapt to various clock domain configurations while maintaining time synchronization accuracy through the consistent use of the buffer intermediary.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10211939B2Apparatus and a method for determining a point in time
Publication Date: 2019.02.19 NAPATECH
  • US10211939B2 patent drawing
  • US10211939B2 patent drawing

AI summary

Forwarding points in time of a clock over a clock boundary is performed by launching the points in time into a buffer, such as a FIFO, in the first clock domain. The oldest point in time is fed into a FIFO or delay line in the other clock domain, which FIFO or delay line comprises a plurality of received points in time, which are shifted through the FIFO or delay line over time. An estimate of a point in time in the second clock domain is derived from a plurality of the points in time in the delay line/FIFO, such as from a mean value thereof. This point in time may be compensated for a known delay in order for this determined point in time to be identical to or close to an actual point in time of the first clock in the first clock domain.