FIFO Queue-Based Command Spreading for Memory Buffer Chip Port Utilization
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Solution Overview
Problem
High-availability memory systems face challenges in maintaining synchronization across different clock domains, leading to issues with command scheduling, power management, and memory throughput due to the asynchronous nature of memory buffer chips and memory controllers.
Innovation Solution
Implementing a first-in-first-out (FIFO) queue-based command spreading mechanism within the memory control unit (MCU) using multiple FIFO queues, each associated with a port on the buffer chip, and an arbitration mechanism with first and second-level priority stages to ensure efficient utilization of the bus and maintain high throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If commands are sent sequentially from the MCU to the buffer chip, then the interface utilization may be maintained, but some ports on the buffer chip may starve and throughput decreases
Solution Approach 1:
The patent segments commands into multiple FIFO queues, with each queue associated with a specific port on the buffer chip. This segmentation allows independent management and scheduling of commands for each port, preventing starvation and improving overall throughput while maintaining manageable complexity through structured organization.
Solution Approach 2:
The patent implements preliminary action by pre-organizing commands in FIFO queues before they are sent to the buffer chip. Commands are sorted and staged in advance according to their destination ports, ensuring that when commands are issued, the buffer chip ports can be efficiently utilized without waiting or starvation.
2Productivity
If multiple command queues are used to manage ports, then port utilization improves, but the number of queues and power consumption increase
Solution Approach 1:
The patent merges the management of multiple ports into a unified FIFO queue structure within the MCU. By consolidating command scheduling into a single integrated system that uses FIFO queues with port associations, the design achieves high port utilization while avoiding the power overhead of completely independent queue management systems for each port.
Solution Approach 2:
The FIFO queue structure serves multiple functions simultaneously: it maintains command ordering, associates commands with specific ports, enables efficient scheduling, and reduces power consumption compared to multiple independent queue systems. This multi-functional design achieves high port utilization without proportional increases in power consumption.
3Adaptability or versatility
If asynchronous design is used between processor and memory buffer chips, then flexibility in frequency selection is improved, but synchronization timing and reliability become more difficult to manage
Solution Approach 1:
The patent introduces an intermediary FIFO queue system that mediates between the asynchronous processor and memory buffer chip. The FIFO queues act as a buffer that decouples the timing requirements of the two components, allowing them to operate at different frequencies while maintaining reliable data transfer and synchronization.
Solution Approach 2:
The FIFO queue structure ensures continuous command flow to the buffer chip ports, maintaining uninterrupted memory operations despite asynchronous timing differences between the processor and memory controller. This continuity preserves synchronization reliability while allowing frequency flexibility.
Data Source
AI summary
Embodiments relate to first-in-first-out (FIFO) queue based command spreading. An aspect includes receiving a plurality of commands by a first level priority stage of a memory control unit (MCU), wherein each of the plurality of commands is associated with one of a plurality of ports located on a buffer chip. Another aspect includes storing each of the plurality of commands in a FIFO queue of a plurality of FIFO queues in the MCU, wherein each of the plurality of commands is assigned to a FIFO queue based on the command's associated port, and each of the plurality of FIFO queues is associated with a respective one of the plurality of ports located on the buffer chip. Another aspect includes selecting a FIFO queue of the plurality of FIFO queues and forwarding a command from the selected FIFO queue to the buffer chip by the second level priority stage. Another aspect includes a third level priority on the buffer chip associated with each respective FIFO queue to help optimize the bandwidth on the returning upstream fetch bus.