Asynchronous FIFO Read Write Counter Circuitry
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Solution Overview
Problem
Asynchronous FIFOs face challenges in providing accurate read and write counts due to the dependency on relative clock frequencies, leading to unreliable estimates of the number of words stored, which is critical for various data processing applications.
Innovation Solution
The implementation of specialized read and write count circuitry in the FIFO memory unit, utilizing shift registers, AND logic, and pulse generators to synchronize count increments and decrements with respective clock signals, ensuring accurate counts even with asynchronous clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FIFO design is used with separate clocks for reading and writing, then asynchronous data transfer between clock domains is enabled, but accurate count of words currently being stored cannot be provided
Solution Approach 1:
The patent divides the counting function into separate read count circuitry and write count circuitry, each operating independently in their respective clock domains. The read count circuitry includes a read count register and associated logic, while the write count circuitry includes a write count register and associated logic. This segmentation allows each counter to be optimized for its specific clock domain while maintaining overall system accuracy.
Solution Approach 2:
The patent introduces cross-clock domain synchronization mechanisms as intermediaries between the read and write operations. These include read-to-write synchronization logic that updates the write count register with accurate information from the read domain, and write-to-read synchronization logic that updates the read count register with accurate information from the write domain. This intermediary approach resolves the counting accuracy problem without requiring the clock domains to be synchronized.
2Productivity
If read and write operations use different clock frequencies, then flexible data transfer rates are achieved, but count delays depend on relative clock frequencies reducing reliability
Solution Approach 1:
The patent implements dynamic counting mechanisms that adapt to varying clock frequencies. The read count circuitry dynamically updates the write count register at rates determined by the read clock frequency, while the write count circuitry dynamically updates the read count register at rates determined by the write clock frequency. This dynamic approach allows the system to maintain accurate counts regardless of the relative frequencies of the read and write clocks, enabling flexible data transfer rates without sacrificing reliability.
3Ease of operation
If status signals Full and Empty are used in conventional FIFOs, then basic status indication is provided, but accurate real-time count of words is not available
Solution Approach 1:
The patent creates accurate copies of the count information through dual registration. The read count register maintains an accurate copy of the number of words in the FIFO from the read perspective, while the write count register maintains an accurate copy from the write perspective. These registers provide precise real-time count information that can be used for flow control, buffer management, and monitoring applications, going beyond the basic Full/Empty status signals.
Data Source
AI summary
A read count circuit and a write count circuit, each for providing a count of data read from or written to, respectively, an asynchronous FIFO memory device. These circuits use read/write clock and read/write enable inputs, the selection of which depend on whether a read or write count is being provided. Essentially, the circuit comprises a shift register having a number of cascaded flip-flops, where the number of flip-flops is based on a ratio of one clock frequency to the other. An AND element at the output of each flip-flop AND's the output of the associated flip-flop with a read/write enable signal. A pulse generator at the output of each AND element synchronizes the outputs of the AND elements with the read/write clock. An adder then sums the outputs of the pulse generators. A counter increments with the adder output and decrements with a read/write enable signal, upon each read/write clock signal, thereby providing a read/write count output.