Cross Clock Domain Interference Cancellation Using FIFO and Adaptive Generator
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Solution Overview
Problem
Conventional methods for cross clock domain interference cancellation, such as the Farrow structure, suffer from substantial computational errors and high complexity, especially when dealing with close clock domains, leading to poor interpolation accuracy and increased computational complexity in systems like HDMI Ethernet channels.
Innovation Solution
An interference cancellation apparatus and method utilizing a First-In-First-Out (FIFO) circuit and a cancellation signal generator to adjust digital transmission signals across clock domains, separating sampled points into integral and decimal portions and applying adaptive algorithms to reduce phase differences and computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the Farrow structure is introduced to process clock domain switching, then interpolation calculation is simplified, but computational errors and bias increase substantially
Solution Approach 1:
The patent extracts the interpolation function from the Farrow structure and implements it separately using a dedicated interpolator circuit. This separates the interpolation operation from the main signal processing path, allowing independent optimization of each function and eliminating the computational errors and bias inherent in the Farrow structure's polynomial combinations.
Solution Approach 2:
The patent introduces an intermediary interpolator circuit that processes the signal between the transmitter and receiver clock domains. This intermediary component performs the interpolation calculation using a separate, optimized path that avoids the polynomial combination limitations of the Farrow structure, thereby improving interpolation accuracy while maintaining simplified processing.
2Measurement precision
If high-order polynomial is used in Farrow structure to improve interpolation accuracy, then computational precision improves, but number of taps increases and computational complexity increases
Solution Approach 1:
The patent segments the interpolation process into discrete, manageable stages using a dedicated interpolator circuit with controlled number of taps. Instead of using a single high-order polynomial with many taps, the interpolation is divided into multiple lower-order operations that can be implemented more efficiently, reducing overall computational complexity while maintaining accuracy.
Solution Approach 2:
The patent changes the parameter representation from high-order polynomial coefficients to a different interpolation approach using a dedicated circuit with adjusted tap parameters. This parameter transformation allows achieving similar or better interpolation accuracy with reduced computational complexity by optimizing the circuit implementation rather than relying on high-order mathematics.
3Adaptability or versatility
If Farrow structure is used for clock domain switching, then data transformation between clock domains is achieved, but time delay in signaling is prolonged
Solution Approach 1:
The patent performs preliminary interpolation calculation before the main signal processing in a dedicated interpolator circuit. By completing the time-domain transformation early in the process, the subsequent signal processing can proceed more quickly, reducing overall signaling time delay while maintaining the necessary clock domain transformation capability.
Solution Approach 2:
The patent replaces the traditional Farrow structure's mechanical polynomial combination approach with a dedicated interpolator circuit implementation. This substitution uses a different physical/computational mechanism that is more efficient in terms of time delay, achieving the same clock domain transformation function with reduced latency.
4Adaptability or versatility
If Farrow structure is introduced to process interpolated data, then clock domain switching is enabled, but multiplication operations become inevitable increasing computational complexity
Solution Approach 1:
The patent extracts the multiplication operations from the Farrow structure and implements them in a dedicated interpolator circuit with optimized arithmetic units. This separation allows the multiplication operations to be performed more efficiently with dedicated hardware resources, reducing overall computational complexity while maintaining clock domain switching capability.
Solution Approach 2:
The patent creates a simplified copy of the interpolation function in a dedicated circuit that avoids the complex polynomial combination requirements of the Farrow structure. This copied implementation achieves the same functional result with fewer and simpler operations, eliminating the need for comprehensive multiplication operations and reducing computational complexity.
Data Source
AI summary
An apparatus and method for cross clock domain interference cancellation is provided to a communication system which includes a transmitter operated in a first clock domain and a receiver operated in a second clock domain. The apparatus comprises a First-In-First-Out (FIFO) circuit and a cancellation signal generator. The FIFO circuit receives a digital transmission signal of the transmitter in the first clock domain, and outputs the digital transmission signal in the second clock domain according to an accumulated timing difference between the first and second clock domains. The cancellation signal generator generates a cancellation signal for canceling an interference signal received by the receiver according to the digital transmission signal outputted by the FIFO circuit. The interference signal is generated in response to the digital transmission signal. The cancellation signal generator adjusts the cancellation signal according to a phase difference between the interference signal and the cancellation signal.