Processor Simulator FIFO Debugging via Data Counting
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Solution Overview
Problem
Debugging communication among units on a processor simulator is challenging due to data transfer mismatches between senders and receivers, especially when there is a lack of data-dependent conditional branch support, leading to blocking issues and cyclic dependencies that make it difficult to identify mismatch locations.
Innovation Solution
A method that counts data written and read through FIFOs, avoids blocking by reading dummy data when FIFOs are empty and discarding data when FIFOs are full, and identifies mismatches by comparing the amounts of data transferred between senders and receivers, allowing for corrective actions such as updating instruction sets or redoing simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If data-dependent conditional branch support is implemented in the processor simulator, then debugging capability is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary component that monitors and tracks data transfers between units without requiring complex conditional branch support. This intermediary mechanism enables debugging by observing FIFO operations and detecting mismatches, thereby improving debugging capability while avoiding the complexity of full conditional branch implementation.
2Productivity
If blocking is avoided by reading dummy data from empty FIFOs, then productivity is improved, but data transfer accuracy deteriorates
Solution Approach 1:
The system performs preliminary actions by pre-filling FIFOs with dummy data before actual data transfer begins. This allows the receiver to continuously read without blocking, maintaining high productivity. The dummy data is later replaced or accounted for, ensuring data transfer accuracy is not compromised.
Solution Approach 2:
The patent employs discarding and recovering by reading dummy data from FIFOs and then replacing it with actual data. The dummy data is discarded once actual data arrives, allowing continuous operation without blocking while maintaining data integrity through proper data replacement and tracking.
3Reliability
If data transfer mismatch detection is implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where the system continuously monitors data transfer operations and provides feedback when mismatches are detected. By counting and comparing data read versus data written, the system reliably detects transfer errors and can trigger appropriate responses, improving data transfer reliability through straightforward monitoring and comparison logic.
Data Source
AI summary
A method is provided for identifying a data transfer mismatch between a sender and a receiver from among units of a software simulator of a hardware processor. The simulator runs the plurality of the units which communicate with each other via First-In First-Outs (FIFOs). The method counts amounts of data the sender writes to the FIFOs and the receiver reads from the FIFOs for a given data transfer. The method avoids blocking during FIFO reading and writing operations by (i) reading dummy data by the receiver, even if the FIFOs are empty, when the receiver tries reading from the FIFOs, and (ii) discarding written data if the FIFOs are full, when the sender tries writing to the FIFOs. The method identifies mismatches in the amount of data the sender writes to the FIFOs versus the amount of data the receiver reads from the FIFOs for the given data transfer.