DRAM Data Recovery via FIFO Buffer and ECC Validation
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Solution Overview
Problem
The existing data interface between a processor system on chip (SOC) and external dynamic random-access memory (DRAM) is prone to errors that cannot be fully corrected by existing error correction codes, leading to potential data corruption and reliability issues.
Innovation Solution
Implementing a method that includes a first-in-first-out (FIFO) data storage structure on the memory controller to store recent data and ECC check bits, generating expected ECC check bits, and using a sideband channel with an I2C protocol to communicate errors and replace corrupted data with stored copies when ECC correction is not possible, and cooperating with the CPU cache coherence hierarchy to find uncorrupted data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard ECC processing is used for data transmission between memory controller and memory device, then data integrity is maintained for correctable errors, but uncorrectable errors cause data loss and system failures
Solution Approach 1:
The patent implements preliminary action by storing a copy of data words in a FIFO buffer before they are written to DRAM. When uncorrectable errors are detected during refresh operations, the system can retrieve the original uncorrupted data from the FIFO buffer, preventing data loss without requiring complex real-time recovery mechanisms.
Solution Approach 2:
The patent applies the copying principle by maintaining duplicate copies of data words in the FIFO buffer while the primary copy resides in DRAM. This redundant storage enables recovery from uncorrectable errors by comparing and replacing corrupted data with the stored copy, significantly improving reliability beyond standard ECC capabilities.
2Reliability
If additional error detection and recovery mechanisms are implemented beyond standard ECC, then robustness against uncorrectable errors is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the memory system to automatically detect, diagnose, and recover from uncorrectable errors using the FIFO buffer and refresh operation mechanisms. The system performs self-diagnosis through ECC validation during refresh and self-repair by retrieving clean copies from the FIFO, eliminating the need for external intervention or complex manual recovery procedures.
Solution Approach 2:
The patent uses periodic action by incorporating error detection and potential recovery operations during regular DRAM refresh cycles. Instead of continuous monitoring, the system validates data integrity periodically during mandatory refresh operations, reducing overhead while maintaining robust error detection and recovery capabilities.
3Reliability
If data validation and recovery operations are performed during memory refresh, then data availability is improved, but processing time and productivity are reduced
Solution Approach 1:
The patent performs error detection and recovery operations periodically during mandatory DRAM refresh cycles rather than during every memory access. This approach leverages existing refresh operations to validate data integrity, minimizing impact on normal memory productivity while ensuring data availability through periodic verification and recovery.
Solution Approach 2:
The patent maintains continuity of useful action by integrating error detection and recovery into the existing DRAM refresh operations. Instead of adding separate validation steps that would interrupt normal memory access, the system performs ECC validation and potential recovery during the continuous refresh cycle, ensuring both data availability and sustained productivity.
Data Source
AI summary
Disclosed is a method of recovering corrupted data, comprising providing a FIFO storage structure on the memory controller, and providing an error correction code (ECC) generator to the memory device, the ECC generator configured to generate ECC check bits based on a data word. For each data word, the method comprises storing a copy of the data word, appended check bits, and associated address into the FIFO storage structure; generating expected check bits based on the data word; when the expected check bits match the appended check bits, storing the data word and appended check bits to the memory device; and when the expected check bits do not match the appended check bits, and an error in the data word is uncorrectable, replacing the data word and appended check bits with the copy of the data word and appended check bits that were stored in the FIFO storage structure.