FIFO Memory with Dual Banks for Clock Domain Crossing
Solution Overview
Problem
Existing FIFO memory circuits on integrated circuits often require higher power supply values and exhibit lower yields when implemented using dual-port static random-access memory, particularly when coordinating operations between different clock domains.
Innovation Solution
The implementation of a first-in-first-out memory circuit using left and right banks of memory, with a write controller and a read controller that coordinate write and read operations by using bank empty flag information and latching the last write address to determine transitions between banks, allowing for efficient data handling across both banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-port static random-access memory is used to implement FIFO circuits, then the interface between circuits operating in different clock domains can be formed, but the yields are lower and higher minimum power supply values are required
Solution Approach 1:
The memory array is divided into two separate banks (first bank and second bank), each operating independently. This segmentation allows the FIFO circuit to avoid the complexities of dual-port memory while achieving the same functionality through coordinated access to two single-port memory banks, thereby improving yield and reducing power supply requirements.
2Adaptability or versatility
If dual-port static random-access memory is used to implement FIFO circuits, then the interface between circuits operating in different clock domains can be formed, but higher minimum power supply values are required
Solution Approach 1:
The memory array is divided into two separate banks (first bank and second bank), each operating independently. This segmentation allows the FIFO circuit to avoid the complexities of dual-port memory while achieving the same functionality through coordinated access to two single-port memory banks, thereby improving yield and reducing power supply requirements.
3Adaptability or versatility
If dual-port static random-access memory is used to implement FIFO circuits, then the interface between circuits operating in different clock domains can be formed, but the yields are lower
Solution Approach 1:
The memory array is divided into two separate banks (first bank and second bank), each operating independently. This segmentation allows the FIFO circuit to avoid the complexities of dual-port memory while achieving the same functionality through coordinated access to two single-port memory banks, thereby improving yield and reducing power supply requirements.
Data Source
AI summary
A first-in-first-out memory may have first and second memory banks. A write controller may write data into the first and second memory banks. In performing write operations, the write controller may determine whether to write the data into the first bank or the second bank by evaluating a first bank empty flag and a second bank empty flag. When transitioning between writing in the first bank and the second bank, the write controller may latch a write address value indicative of the last location at which valid data was written in a given bank. A read controller may read data from the first and second memory bank. The read controller may determine when to transition between reading in the first bank and reading in the second bank by comparing a current read address to the latched write address value.