Adjustable Empty Threshold Limit for FIFO Circuits
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Solution Overview
Problem
PCI Express devices face data transmission throughput issues due to frequent link speed negotiations, which put them in an idle mode for long periods, affecting data transmission efficiency in asynchronous FIFO circuits operating between different clock frequency domains.
Innovation Solution
An adjustable empty threshold limit for FIFO circuits is introduced, allowing the control logic to adjust the threshold based on changing clock frequencies, ensuring data transmission only when a sufficient difference between write and read pointers exceeds the adjusted threshold, thereby optimizing data transfer across different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the empty threshold limit is fixed, then the FIFO circuit operation is simple, but data transmission throughput decreases due to long idle periods during link speed negotiation
Solution Approach 1:
The empty threshold limit is made dynamic rather than fixed. The control logic circuit adjusts the empty threshold limit based on the clock frequency of the second clock signal, which varies during link speed negotiation. This dynamic adjustment allows the FIFO circuit to adapt to different operating conditions, reducing idle periods and improving data transmission throughput without requiring a completely complex reconfiguration of the FIFO structure.
Solution Approach 2:
The empty threshold limit parameter is changed based on clock frequency conditions. When the second clock signal frequency changes (indicating link speed negotiation), the control logic circuit modifies the empty threshold limit value accordingly. This parameter change optimizes the pointer difference threshold for data transmission, allowing faster resumption of data flow after negotiation events.
2Productivity
If the empty threshold limit is adjusted dynamically, then data transmission efficiency improves, but the control logic complexity increases
Solution Approach 1:
The control logic circuit implements feedback by monitoring the clock frequency of the second clock signal and adjusting the empty threshold limit accordingly. This closed-loop control ensures that the FIFO circuit operates optimally under varying link speed conditions without requiring complex manual intervention or preconfiguration, balancing improved efficiency with manageable control logic complexity.
3Adaptability or versatility
If the FIFO circuit operates with fixed clock frequencies, then the circuit design is simpler, but adaptability to link speed changes is reduced
Solution Approach 1:
The FIFO circuit is designed to dynamically adapt to changing clock frequencies through the control logic circuit that adjusts the empty threshold limit based on the second clock signal frequency. This dynamic design enables the circuit to handle link speed negotiations and varying operational conditions effectively.
Solution Approach 2:
The FIFO circuit design incorporates multi-functionality by handling both fixed and variable clock frequency operations through a single unified structure. The control logic circuit provides universal adaptability across different link speeds and operating conditions, eliminating the need for multiple specialized FIFO circuits for different scenarios.
Data Source
AI summary
In one embodiment, transceiver circuitry includes a first-in-first-out (FIFO) circuit and a control logic circuit. The FIFO circuit receives data signals based on a first clock frequency and outputs stored data signals based on a second clock frequency. The stored data signals are transmitted out of the FIFO circuit only in response to a difference between a value of a write pointer of the FIFO circuit and a value of a read pointer of the FIFO circuit exceeding an empty threshold limit of the FIFO circuit. The control logic circuit may be utilized to adjust the empty threshold limit of the FIFO circuit.