FIFO Memory Error Detection Using Asynchronous Pointer Sampling

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Solution Overview

Problem

Existing memory systems struggle to detect FIFO overflow and underflow error conditions in advance, leading to data transmission errors, as previous methods require synchronized write and read pointer frequencies and only detect errors after they occur, resulting in potential data corruption.

Innovation Solution

The implementation of a FIFO memory error detection system that uses minimal additional circuitry to detect overflow and underflow conditions independently of write and read pointer clock frequencies, allowing for advance warning and intervention to prevent data corruption, using binary and one-hot encoding for write and read pointers respectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If synchronized write and read pointer frequencies are used for error detection, then error detection capability is improved, but system complexity and clock synchronization requirements worsen

Engineering Contradiction:
Improveerror detection capabilityVSAvoidclock synchronization requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error detection function is segmented into independent logical operations: sampling the write pointer value, comparing it with threshold values (first and second threshold), and generating error signals. This segmentation allows each operation to be performed independently without requiring synchronized clock frequencies between write and read sides.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Threshold values serve as intermediaries between the write pointer and the error detection logic. By comparing the write pointer against predetermined thresholds rather than directly synchronizing with the read pointer, the system mediates the frequency difference between write and read clocks while still detecting potential overflow conditions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If error detection is performed after error occurrence, then detection simplicity is improved, but data corruption risk worsens

Engineering Contradiction:
Improvedetection simplicityVSAvoiddata corruption risk
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The system performs preliminary error detection by sampling the write pointer and comparing it against threshold values before actual overflow or underflow errors occur. This preliminary action generates advance warning signals that allow the system to take preventive measures before data corruption happens.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The error detection mechanism takes preliminary anti-action by detecting potential error conditions and generating warning signals before the actual harmful effect (data corruption) occurs. This allows the system to counteract potential errors before they manifest as actual data loss or corruption.

Inventive Principle:
Principle #9Preliminary anti-action

3Object-affected harmful factors

If advance error detection is implemented, then data corruption prevention is improved, but additional circuitry requirements worsen

Engineering Contradiction:
Improvedata corruption preventionVSAvoidadditional circuitry
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The system implements partial error detection by monitoring only critical threshold conditions (overflow and underflow boundaries) rather than continuously analyzing all possible error states. This partial action provides sufficient protection against data corruption while minimizing the additional circuitry required.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The error detection mechanism changes parameters by using predetermined threshold values that can be configured based on FIFO depth requirements. By parameterizing the threshold values rather than hardcoding complex detection logic, the system achieves data corruption prevention with minimal and configurable additional circuitry.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11960731B2FIFO memory error condition detection
Publication Date: 2024.04.16 MICRON TECHNOLOGY INC
  • US11960731B2 patent drawing
  • US11960731B2 patent drawing
  • US11960731B2 patent drawing

AI summary

An apparatus can include first circuitry coupled to a FIFO memory. The first circuitry can provide a write pointer of the FIFO memory at a first rate. Second circuitry can be coupled to the FIFO memory. The second circuitry can provide a read pointer of the FIFO memory at a second rate that is different from the first rate. Third circuitry can be coupled to the first and second circuitries. The third circuitry can provide an indication of an error condition of the FIFO memory based on the write pointer and the read pointer.