Asynchronous FIFO Error Detection in Semiconductor ICs
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Solution Overview
Problem
Conventional semiconductor integrated circuits cannot distinguish between transmission errors and internal component errors, and are unable to detect errors occurring in the FIFO, leading to inefficiencies in abnormality detection.
Innovation Solution
Incorporating a test circuit with a PLL circuit and an asynchronous FIFO, where a test pattern is supplied as interrupt data to detect abnormalities based on the relation between output data and expected values, allowing for the detection of errors in both the FIFO and PLL circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a judgment unit monitors received data to detect abnormalities, then reliability is improved, but the ability to distinguish between transmission errors and internal component errors deteriorates
Solution Approach 1:
The detection function is segmented into multiple specialized units: a transmission error detection unit that monitors transmission lines, and an internal error detection unit that monitors internal components like FIFO. This segmentation allows each unit to specialize in detecting specific types of errors, thereby improving both reliability and measurement precision simultaneously.
Solution Approach 2:
The patent introduces an internal error detection unit as an intermediary component that specifically monitors data within internal components. This intermediary unit acts as a bridge between the data flow and the error detection system, enabling precise identification of internal errors without affecting the overall reliability of the abnormality detection system.
2Measurement precision
If error-check values are embedded in data by the transmitter, then transmission error detection is improved, but the ability to detect errors in the FIFO deteriorates
Solution Approach 1:
The error detection system is segmented into two independent parts: one that handles transmission error detection using embedded error-check values, and another that handles internal component error detection by monitoring data integrity within the FIFO. This segmentation ensures that each detection method operates independently and effectively for its specific target.
Solution Approach 2:
The internal error detection unit is designed with multi-functionality, capable of detecting both transmission errors that penetrate through to internal storage and errors that originate within the FIFO itself. This universal detection capability ensures comprehensive error coverage without compromising specialized detection methods.
3Device complexity
If conventional abnormality detection methods are used, then implementation simplicity is maintained, but the ability to detect errors in asynchronous FIFO deteriorates
Solution Approach 1:
An internal error detection unit is introduced as an intermediary component between the FIFO and the existing judgment unit. This intermediary unit adds minimal complexity by interfacing with the existing system architecture while providing enhanced FIFO error detection capability through targeted monitoring of data integrity within the FIFO.
Solution Approach 2:
The detection system is enhanced to include self-monitoring capabilities where the internal error detection unit continuously monitors data integrity within the FIFO without requiring external intervention. This self-service approach maintains system simplicity while improving detection accuracy through autonomous error identification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective detection of abnormalities in the asynchronous FIFO and PLL circuit, improving the reliability of semiconductor integrated circuits by distinguishing between transmission and internal errors.
Implementation Method 1
a PLL circuit structured to frequency multiply a write clock so as to generate a read clock
Data Source
AI summary
An asynchronous FIFO is arranged between an input bus and an output bus with a different number of lanes. The asynchronous FIFO supplies a write clock and a read clock. A circuit block receives output data from the asynchronous FIFO via the output bus, and executes predetermined processing. In a test mode, a test circuit supplies a test pattern as interrupt data to the input bus, and detects the presence or absence of an abnormality based on a relation between the output data and its expected value based on the test pattern.