Dynamic Power Scaling via FIFO Fill Level Monitoring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional wireless integrated circuits face challenges in minimizing power consumption, as existing methods for configuring power modes do not directly align with the required processing capabilities of transmit and receive circuitry, leading to inefficient power management.
Innovation Solution
The integration of dynamic power control circuitry that adjusts the operating frequency and power supply voltage of processing modules based on fill level information from input and output FIFOs, allowing for real-time performance adjustments to optimize power consumption according to FIFO fill levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If static voltage scaling is used to minimize power consumption, then power consumption is reduced, but processing capability cannot be adjusted during normal operation
Solution Approach 1:
The patent implements dynamic voltage scaling by introducing a control mechanism that adjusts the operating voltage of processing tiles in real-time based on system conditions. The controller monitors FIFO fill levels and dynamically modifies voltage supply to processing tiles, transitioning from static pre-configured voltage levels to adaptive voltage adjustment during operation. This resolves the contradiction by enabling both power consumption reduction and processing capability adjustment throughout normal operation.
2Use of energy by stationary object
If high level system software is used to configure different power modes, then power management is enabled, but power modes are not directly linked to required processing capability
Solution Approach 1:
The patent establishes a feedback loop where the controller continuously monitors FIFO fill levels and uses this information to adjust power modes of processing tiles. The system reads fill level data from FIFO structures, compares current processing demand with available capacity, and dynamically configures power modes accordingly. This direct feedback mechanism ensures power management decisions are tightly coupled with actual processing capability requirements, eliminating the disconnect present in software-controlled approaches.
Solution Approach 2:
The system enables processing tiles to self-regulate their power consumption based on actual workload demands. Each processing tile's power mode is automatically adjusted by the controller based on real-time FIFO fill level monitoring, without requiring external software intervention or manual configuration. The processing capability and power consumption are directly aligned through this self-service mechanism where the system adapts to its own operational state.
3Productivity
If processing module performance is increased to handle high data rates, then data processing capability is improved, but power consumption increases
Solution Approach 1:
The patent changes the operating parameters of processing tiles dynamically by adjusting voltage levels based on data processing demands. When FIFO fill levels indicate high processing requirements, the controller increases voltage to enhance processing speed and capability. When data rates are lower, the controller reduces voltage to minimize power consumption. This parameter adjustment strategy enables the system to achieve high data processing capability only when necessary, otherwise operating at lower power consumption levels.
Data Source
AI summary
Integrated circuits with wireless communications circuitry are provided. The wireless communications circuitry may include an input FIFO, an output FIFO, a processing module interposed between the input and output FIFOs, and dynamic power control circuitry that controls the performance of the processing module. The input and output FIFOs may provide fill level information to the processing module. The dynamic power control circuitry may analyze the current fill level information received from the input and output FIFOs and may increase the operating frequency and/or boost the power supply voltage of the processing module in response to detecting that the input FIFO is filling up faster than the output FIFO or may decrease the operating frequency and/or reduce the power supply voltage of the processing module in response to detecting that the output FIFO is filling up faster than the input FIFO.