Synchronous FIFO Using Distributed Flip-Flops to Reduce Chip Area
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Solution Overview
Problem
The existing design of synchronous First-In-First-Out (FIFO) modules in digital circuits, particularly in Field-Programmable Gate Arrays (FPGAs), relies on Random Access Memory (RAM) which leads to resource wastage and increased chip area and power consumption due to the limited size of RAM resources, especially when implementing multiple FIFOs with small storage depths.
Innovation Solution
A synchronous FIFO design that utilizes N alternately connected registers, multiplexers, and deciders, along with indication circuits, to manage data storage and output without relying on RAM, thereby reducing resource usage and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If RAM is used for FIFO storage design, then data storage function is achieved, but chip area and power consumption increase
Solution Approach 1:
The patent divides the storage function into multiple distributed flip-flops (N first flip-flops) instead of using a single RAM block. Each flip-flop stores one bit of data, and together they provide the required storage capacity. This segmentation allows the storage function to be distributed across the chip, reducing the concentrated area occupation and allowing better spatial utilization.
Solution Approach 2:
The patent extracts the storage function from dedicated RAM resources and implements it using basic logic elements (flip-flops, multiplexers, and logic gates) that are more abundantly available in FPGA devices. By taking out the storage function from RAM and implementing it with primitive logic elements, the design avoids the area overhead associated with RAM blocks.
2Quantity of substance
If RAM is used for FIFO storage design, then data storage function is achieved, but power consumption increases
Solution Approach 1:
The patent extracts the storage function from power-hungry RAM blocks and implements it using low-power flip-flops and logic gates. By using basic logic elements that have lower static and dynamic power consumption compared to RAM blocks, the design achieves the storage function with reduced power consumption.
Solution Approach 2:
The patent uses simple, low-cost logic elements (flip-flops, multiplexers, logic gates) instead of expensive RAM blocks. These basic elements consume less power and are more suitable for implementing small-depth FIFOs where the overhead of RAM blocks would be excessive.
3Quantity of substance
If RAM resources are used, then storage function is achieved, but resource wastage occurs when multiple small-depth FIFOs are needed
Solution Approach 1:
The patent segments the storage function into individual flip-flops that can be independently configured. This segmentation allows the same basic structure to be scaled to different depths by simply changing the value of N, making the design highly adaptable to different FIFO depth requirements without wasting resources.
Solution Approach 2:
The patent creates a universal FIFO structure that can be configured for different depths and applications by adjusting the parameter N. The same basic architecture (flip-flops, multiplexers, logic gates) serves multiple purposes and can be instantiated multiple times without resource wastage, providing high versatility for implementing multiple FIFOs of different sizes.
4Quantity of substance
If RAM is used for FIFO storage, then storage function is achieved, but layout and wiring complexity increases
Solution Approach 1:
The patent segments the storage function into distributed flip-flops that can be placed throughout the chip fabric. This segmentation allows the backend placement and routing tools to distribute the logic elements more evenly across the chip, reducing wire lengths and improving timing closure compared to concentrating all storage in a single RAM block.
Data Source
AI summary
Provided is a synchronous FIFO, including a data storage circuit, a first logic circuit, a second logic circuit and indication circuits. The data storage circuit includes N first registers, N first multiplexers and N first deciders, where N is a positive integer; and the N first registers and the N first multiplexers are alternately connected. Based on the registers, the synchronous FIFO builds a storage required by the FIFO, and primarily includes the registers, the multiplexers and the deciders, the use of an RAM is avoided, that is, there is no need to occupy the RAM, and there is no need to perform RAM read-write enabling and address control, thereby avoiding wasting RAM resources. In designs with lower storage depth requirements, few resources are occupied, so that a chip area is greatly reduced, the cost is reduced, and layout and wiring are more convenient.