Synchronous FIFO with Segmented Head and Tail Registers
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Solution Overview
Problem
Synchronous FIFO memories face limitations in operating speed due to large setup time requirements and signal propagation delays, which restrict the time available for external circuitry to supply and capture data, leading to undesirable low circuit operating speeds.
Innovation Solution
A novel synchronous FIFO design that includes a push signal input lead, pop signal input lead, full signal output lead, valid signal output lead, input data leads, output data leads, a tail register, a head register, and a control circuit that controls the head and internal registers, allowing direct writing into the head or tail register, simultaneous pushing and popping, and efficient data propagation without the need for output multiplexing or large fanout circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional synchronous FIFO design is used with multiple internal registers and output multiplexing, then data storage capacity is improved, but signal propagation delays and setup time requirements increase
Solution Approach 1:
The FIFO is segmented into distinct functional regions: a head register for output, a tail register for input, and multiple internal registers for storage. This segmentation allows data to flow through dedicated paths, reducing propagation delay while maintaining storage capacity. The head register directly connects to output data leads, and the tail register directly connects to input data leads, eliminating multiplexing delays.
Solution Approach 2:
The head register and tail register act as intermediary elements between the external circuitry and the internal storage registers. The head register mediates the output path by directly driving output data leads without multiplexing, while the tail register mediates the input path by directly receiving input data. This intermediary structure reduces setup time requirements for external circuitry.
2Reliability
If conventional synchronous FIFO design with large fanout circuitry is used, then reliability is improved, but device complexity increases
Solution Approach 1:
The complex output multiplexing circuitry and large fanout structures are extracted and replaced with a simplified architecture. The head register directly drives the output data leads without requiring multiplexers, and the tail register directly receives input data without complex fanout. This extraction of unnecessary complexity maintains reliability while significantly reducing device complexity.
Solution Approach 2:
Instead of using a single central register that multiplexes data to multiple outputs (conventional approach), the patent inverts the architecture by having multiple internal registers feed into dedicated head and tail registers that directly drive inputs and outputs. This inverted structure eliminates the need for complex multiplexing and fanout circuitry.
3Reliability
If push setup time requirements are large, then data integrity is improved, but circuit operating speed decreases
Solution Approach 1:
The tail register is prepared in advance to directly receive input data from the input data leads on the clock edge. By having the tail register positioned and configured beforehand to directly accept data, the setup time requirement for external circuitry is minimized while ensuring data integrity through the registered interface.
Solution Approach 2:
The tail register creates a copied interface to the input data leads, providing a registered copy of the input data that can be captured on the clock edge. This copying mechanism ensures data integrity through proper synchronization while reducing setup time requirements for the external circuitry that drives the input data leads.
4Reliability
If pop setup time requirements are large, then data capture reliability is improved, but circuit operating speed decreases
Solution Approach 1:
The head register is prepared in advance to directly drive the output data leads on the clock edge. By having the head register positioned and configured beforehand to directly output data, the setup time requirement for external circuitry to capture the data is minimized while ensuring reliable data capture through the registered interface.
Solution Approach 2:
The head register creates a copied interface to the internal storage registers, providing a registered copy of the oldest data value that can be captured on the clock edge. This copying mechanism ensures data capture reliability through proper synchronization while reducing setup time requirements for the external circuitry that captures the output data.
Data Source
AI summary
A registered synchronous FIFO has a tail register, internal registers, and a head register. The FIFO cannot be pushed if it is full and cannot be popped if it is empty, but otherwise can be pushed and/or popped. Within the FIFO, the internal signal fanout of incoming data circuitry and push control circuitry and is minimized and remains essentially constant regardless of the number of registers of the FIFO. The output delay of the output data also is essentially constant regardless of the number of registers of the FIFO. An incoming data value can only be written into the head or tail. If a data value is in the tail and one of the internal registers is empty, and if no push or pop is to be performed in a clock cycle, then nevertheless the data value in the tail is moved into the empty internal register in the cycle.