Host Coprocessor Synchronization via FIFO Event Commands
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Solution Overview
Problem
Existing methods for synchronizing host and coprocessor actions in multi-thread program execution are either costly in terms of hardware utilization or execution time, particularly when relying on hardware interrupts or message passing interface (MPI) protocols.
Innovation Solution
Implementing a First-In-First-Out (FIFO) memory system to store event commands and coprocessor instructions, where the host processor writes entries to the FIFO with an event command at the head, and coprocessors maintain a current event register, allowing for synchronized execution without interrupts and avoiding MPI execution speed penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware interrupts are used to synchronize host and coprocessor actions, then synchronization reliability is improved, but hardware utilization cost increases
Solution Approach 1:
A FIFO buffer is introduced as an intermediary data structure between the host processor and coprocessor. The host writes commands and data to the FIFO, and the coprocessor reads from it, eliminating the need for hardware interrupts while maintaining reliable synchronization through structured data exchange.
Solution Approach 2:
The patent replaces the mechanical hardware interrupt system with a software-based message passing mechanism using FIFO buffers. This substitution eliminates the need for interrupt hardware while achieving the same synchronization goal through structured data exchange protocols.
2Adaptability or versatility
If MPI protocol is used for synchronization, then coordination capability is improved, but execution speed decreases
Solution Approach 1:
The patent extracts only the essential synchronization and command passing functions from complex MPI protocols, implementing a simplified FIFO-based message passing mechanism. This extraction maintains adequate coordination capability while eliminating the execution overhead of full MPI protocol processing.
Solution Approach 2:
The patent changes the parameter of communication protocol complexity from high (MPI) to low (FIFO-based), achieving the same synchronization goal with significantly reduced execution overhead by using simpler data structures and exchange mechanisms.
3Measurement precision
If continuous synchronization monitoring is implemented, then synchronization accuracy is improved, but processing overhead increases
Solution Approach 1:
The host processor performs preliminary actions by writing all necessary commands and data to the FIFO buffer before the coprocessor begins execution. This eliminates the need for continuous monitoring during execution, as the coprocessor simply reads from the pre-prepared FIFO buffer at its own pace.
Solution Approach 2:
The coprocessor autonomously reads from and executes commands in the FIFO buffer without requiring continuous host intervention or monitoring. This self-service mechanism maintains synchronization accuracy while minimizing processing overhead, as each processor operates independently based on the FIFO protocol.
Data Source
AI summary
A method of synchronizing thread execution of a host and one or more coprocessors includes writing by the host of an event command and at least one coprocessor instruction to a FIFO and comparing of the event command with a current event register of the coprocessor until they match, whereupon the FIFO entries are popped and the instructions are forwarded to the coprocessor for execution. A plurality of entry groups can be written to the FIFO, each beginning with an event command. The instructions can direct the coprocessor to exchange data with shared memory and apply its thread to the received data. The processors and shared memory can be linked by a ring-type bus having a controller that performs the comparison, popping, and instruction forwarding. The coprocessor clears the current event register during thread execution, and then writes an event command to the register when processing is complete.