Asynchronous FIFO Buffering via Idle Block Removal
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Solution Overview
Problem
Conventional asynchronous FIFOs in integrated circuits face complexity in synchronizing and decoding independently clocked ports, requiring additional circuitry and engineering effort to manage variations in clock signals, and often result in inefficiencies in data transfer between different clock domains.
Innovation Solution
A circuit and method that removes idle data blocks from a first clock domain stream, inserts idle blocks in the second clock domain stream to maintain a continuous data flow, and employs near-empty signals to prevent memory depletion, allowing asynchronous data transfer without the need for additional decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional asynchronous FIFO implementation is used with two independently clocked ports, then data transfer between different clock domains is enabled, but device complexity increases significantly due to additional circuitry for synchronizing and decoding the two ports
Solution Approach 1:
The patent extracts and removes idle data blocks from the data stream before writing to the FIFO memory. By eliminating idle blocks at the source (write side), the system reduces the burden on the read side and eliminates the need for complex idle block insertion circuitry, thereby reducing overall device complexity while maintaining asynchronous transfer capability
Solution Approach 2:
Instead of inserting idle blocks at the read side to maintain continuous output (conventional approach), the patent inverts the approach by removing idle blocks at the write side before storage. This reversal of the idle block handling approach simplifies the read side circuitry and reduces the need for additional synchronization mechanisms
2Productivity
If idle data blocks are removed or inserted based on FIFO fullness or emptiness, then data flow continuity is maintained, but device complexity increases due to variable increment address counters and additional control circuitry
Solution Approach 1:
The patent performs preliminary action by removing idle data blocks at the write side before data is stored in the FIFO. This advance handling of idle blocks eliminates the need for complex variable increment address counters and idle block insertion circuitry at the read side, reducing control circuit complexity while maintaining efficient data transfer
Solution Approach 2:
The write side circuit autonomously identifies and removes idle data blocks without requiring feedback or coordination from the read side. This self-service approach eliminates the need for complex inter-side communication and control circuitry, reducing overall device complexity while maintaining productivity
3Reliability
If the read side circuit knows the status of the write side circuit to prevent memory from becoming empty, then data integrity is maintained, but device complexity increases due to additional status monitoring and coordination requirements
Solution Approach 1:
By extracting and removing idle data blocks at the write side before storage, the patent ensures that only valid data is written to the FIFO. This eliminates the need for the read side to monitor write side status to prevent empty conditions, thereby maintaining data integrity while reducing status monitoring complexity
Data Source
AI summary
A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of consecutive sequence ordered sets, from the stream of data blocks to create a first modified data stream which is coupled to a memory device. Finally, a second circuit coupled to the memory device generates a second modified data stream using a second clock signal. The second modified data stream preferably comprises the data blocks of the first modified data stream and idle data blocks inserted among the data blocks of the first modified data stream. Methods of buffering data received in a first clock domain and output in a second clock domain are also disclosed.