FIFO Input Queuing System with Priority Output Segmentation

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Solution Overview

Problem

Existing priority queuing systems in networked computer systems often result in high-priority packets being blocked by lower-priority packets due to limited hardware resources and increased complexity, leading to inefficient packet transmission and high costs.

Innovation Solution

Implementing a queuing system with a simple first-in-first-out (FIFO) input queue and output queues for each priority level, where the output port stops accepting packets until all queues have space for at least one packet of each priority, or until only lower-priority packets are ahead, ensuring that high-priority packets are transmitted promptly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single input queue is used without separate priority queues, then hardware complexity and cost are reduced, but high-priority packets are blocked by lower-priority packets

Engineering Contradiction:
Improvequeue structure complexityVSAvoidhigh-priority packet transmission latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent segments the output queuing function by creating separate output queues for different packet priorities at the output port, while maintaining a unified input queue. This segmentation allows high-priority packets to be transmitted separately from low-priority packets, preventing blocking without requiring separate input queues for each priority level.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary mechanism at the output port that mediates between the single input queue and multiple output queues. The output port includes logic to determine packet priority and route packets to appropriate output queues, enabling priority-based transmission while using a single input queue structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If multiple parallel input queues are used (one for each priority), then high-priority packet transmission is improved, but hardware cost and implementation complexity increase

Engineering Contradiction:
Improvehigh-priority packet transmission latencyVSAvoidinput queue structure complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent merges multiple priority-specific input queues into a single unified input queue, eliminating the need for complex queue management logic at the input port. The simplification is compensated by priority handling logic at the output port, which maintains the ability to prioritize packet transmission without requiring multiple input queues.

Inventive Principle:
Principle #5Merging (Combining)

3Loss of time

If extensive buffering with one output queue per priority per input port is used, then packet blocking is reduced, but hardware cost becomes unacceptably expensive as switch ports grow

Engineering Contradiction:
Improvepacket blocking durationVSAvoidbuffering structure complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies segmentation to the output buffering function by creating separate output queues for different priorities, but only at the output port level rather than at every input port. This reduces the total number of queues from (input ports × output ports × priorities) to (output ports × priorities), significantly reducing hardware requirements while maintaining priority-based transmission.

Inventive Principle:
Principle #1Segmentation

4Loss of time

If separate input queues for each priority are implemented, then high-priority packet handling is improved, but memory buffer usage efficiency decreases

Engineering Contradiction:
Improvehigh-priority packet transmission latencyVSAvoidmemory buffer utilization efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent merges all priority-level packet buffering into a single shared input queue structure, allowing memory buffers to be used efficiently across all priorities. The single input queue can hold packets of any priority, maximizing buffer utilization while the output port logic ensures high-priority packets are transmitted first when available.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7778168B1Queuing system with mechanism to limit blocking of high-priority packets
Publication Date: 2010.08.17 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US7778168B1 patent drawing
  • US7778168B1 patent drawing
  • US7778168B1 patent drawing

AI summary

A method, computer program product, and queuing system for queuing prioritized items (such as network packets), which limits the degree to which higher-priority queue items are blocked by lower priority queue items, is disclosed. A preferred embodiment of the present invention uses a simple first-in-first-out (FIFO) queue as an input queue, along with an output queue corresponding to each packet priority. A strategy is applied at the output queues to guarantee that blocking of high-priority queue items in the input queue will be limited in duration. One disclosed strategy is to enforce a constraint that whenever an output queue of any priority becomes full, the output port will stop accepting packets of any priority until all queues have space for at least one packet of each priority. Another strategy is for the output port to stop accepting packets having priorities greater than or equal to the priority of the full queue.