Configurable IC Computing Unit With FIFO Input Synchronization
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Solution Overview
Problem
Configurable integrated circuits face challenges in stabilizing and synchronizing input data for complex calculations, leading to potential erroneous results and inefficient resource utilization due to the complexity of implementing delays or trigger times in data flow management.
Innovation Solution
A calculation unit with a First In First Out (FIFO) buffer memory associated with each input to store incident data, allowing for autonomous data validity signal detection and storage, enabling data transmission only when valid, and triggering operations when all necessary data is stored, thus ensuring stability and synchronization without waiting periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay is inserted between two successive calculation units to ensure data stability and synchronization, then the stability and synchronization of input data are improved, but the hardware resources are increased and the device complexity is worsened
Solution Approach 1:
The calculation unit autonomously manages its own input data stability and synchronization by using its reception memory to store incident data and trigger operations when data is ready, eliminating the need for external delay mechanisms or complex orchestration of trigger times across multiple units
Solution Approach 2:
The reception memory is associated with each input independently, allowing each input to be managed separately and autonomously, which simplifies the overall system architecture compared to global delay mechanisms
2Reliability
If trigger times are defined for each computing unit to manage data stability and synchronization, then the stability and synchronization of input data are improved, but the data flow configuration complexity is increased and flexibility is reduced
Solution Approach 1:
Each calculation unit independently determines when its input data is stable and ready by monitoring its own reception memory, eliminating the need for external orchestration of trigger times and reducing configuration complexity
Solution Approach 2:
The operation triggering is dynamic and adaptive, automatically activating when data becomes available in the reception memory rather than following a predetermined static schedule, which improves flexibility
3Reliability
If delay mechanisms are implemented to ensure data stability, then the stability of input data is improved, but the calculation unit availability and productivity are reduced due to waiting periods
Solution Approach 1:
The reception memory stores incident data in advance before the calculation unit needs to process it, so that when the unit is ready, the data is already available and stable, eliminating waiting periods and improving productivity
Solution Approach 2:
The calculation unit can continuously process data as it becomes available without idle waiting periods, since the reception memory ensures data readiness, maximizing resource utilization
Data Source
Figure 1A~2A
Figure 2B~3A
Figure 3B~4
AI summary
A processing unit (PU) of a configurable integrated circuit includes a data input (10), an output (11), and a core (100) configured to perform an operation on at least one data point to obtain a result, and transmit the result to the output (11). The PU further includes a First-In, First-Out memory (12) associated with each input (10) and configured to store each data point received by that input. The PU triggers the storage of data when a predefined value validity signal is detected, transmits stored data to the core (100), and triggers the execution of the operation when data is stored in each memory point (12) and when no operation is currently being executed. The PU transmits a predefined value validity signal to the output simultaneously with each transmitted result, and a different signal otherwise.This facilitates the management of synchronization and the stabilization of input data.