Asynchronous Synchronous Interface FIFO Memory Decoding
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Solution Overview
Problem
Interfacing asynchronous communication systems with synchronous communication systems within integrated circuits poses challenges due to propagation delays and synchronization issues, particularly in systems-on-chip for mobile and multimedia applications.
Innovation Solution
An interface system that writes data from asynchronous circuits to a First-In First-Out (FIFO) memory asynchronously and reads data synchronously in response to a clock signal, using sub-circuits for decoding and converting between two-phase and four-phase signaling protocols to prevent delays and optimize data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous communication is used for interconnection within integrated circuits, then delay insensitivity is improved, but synchronization with synchronous components deteriorates
Solution Approach 1:
The patent introduces a FIFO buffer as an intermediary component between asynchronous and synchronous communication domains. The FIFO buffer receives data asynchronously from the asynchronous domain and provides data synchronously to the synchronous domain, effectively mediating the interface between these two different communication paradigms and resolving the contradiction between delay insensitivity and synchronization capability
Solution Approach 2:
The interface system is segmented into distinct asynchronous and synchronous domains, each handling communication in its native protocol. The FIFO buffer acts as a boundary that separates these domains, allowing each to operate independently with optimal characteristics while still enabling intercommunication
2Adaptability or versatility
If synchronous communication protocol is used, then synchronization with clock signal is improved, but propagation delays worsen
Solution Approach 1:
The FIFO buffer serves as a mediator that absorbs propagation delays within the synchronous domain without affecting the asynchronous domain. By buffering data, the system can tolerate variations in propagation delay while maintaining synchronization with the clock signal
3Adaptability or versatility
If interface system converts between two-phase and four-phase signaling protocols, then compatibility between different protocols is improved, but device complexity worsens
Solution Approach 1:
The FIFO buffer acts as an intermediary that simplifies protocol conversion by providing a standardized interface. Rather than implementing complex direct conversion logic between two-phase and four-phase protocols, the system uses the FIFO buffer as an intermediate storage element that naturally handles the protocol differences
Solution Approach 2:
The interface system changes the temporal parameters of data representation by storing data in the FIFO buffer at different clock rates and phases. This parameter transformation allows compatibility between protocols with different signaling phases without requiring complex conversion circuitry
Data Source
AI summary
An interface system for interfacing an asynchronous circuit with a synchronous circuit, wherein the synchronous circuit samples, in response to a clock signal, a first data signal when a first control signal indicates that the first data signal contains valid data, and wherein the asynchronous circuit generates a second data signal according to an asynchronous communication protocol. The system includes a FIFO memory, a control circuit for asynchronously writing the second data signal in the memory when the second data signal indicates the start of a communication, and synchronously reading the second data signal from the memory in response to a clock signal, and a conversion circuit for decoding, according to a asynchronous communication protocol, the second data signal read from the memory in a decoded data signal, wherein the decoded data signal corresponds to the first data signal.