Processor Coprocessor FIFO Interface Hardware Signals
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Solution Overview
Problem
Current techniques for connecting processor cores to coprocessors are suboptimal due to issues with dark silicon and reduced system throughput, particularly in handling backlogs and deferring coprocessor work, and involve complex coordination logic and increased power consumption.
Innovation Solution
The use of dedicated hardware signals to manage a first-in first-out (FIFO) structure that facilitates the transfer of control information and data between multiple computational processors, allowing for efficient push, pop, and peek transactions, and managing contention through serialization of operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If direct connection between core and coprocessor is used, then simple interface is achieved, but system throughput is reduced due to dark silicon and inability to handle backlog
Solution Approach 1:
A FIFO buffer is introduced as an intermediary component between the processor core and coprocessor. The FIFO decouples the core from the coprocessor, allowing the core to write work items to the FIFO without waiting for coprocessor completion. This enables the core to continue executing other instructions while the coprocessor processes work items at its own pace, eliminating dark silicon and improving system throughput without significantly increasing interface complexity.
2Productivity
If common memory with work queue is used, then backlog handling is improved, but coordination logic complexity and power consumption increase
Solution Approach 1:
The coordination logic is extracted from the processor core and implemented as dedicated hardware signals within the FIFO interface. Instead of requiring the core to poll configuration registers or manage work queue coordination through complex software logic, the FIFO includes dedicated push and pop signals that automatically manage work item transfer. This extraction of coordination logic from the core reduces both the complexity of coordination logic and power consumption while maintaining backlog handling capability.
3Device complexity
If coprocessor executes one unit of work at a time, then simple coprocessor architecture is maintained, but system throughput is reduced
Solution Approach 1:
The FIFO buffer pre-stores multiple work items before the coprocessor begins execution. The core can populate the FIFO with multiple work items in advance, creating a backlog of pending operations. The coprocessor then executes these pre-loaded work items sequentially without requiring complex multi-threading or interrupt handling, maintaining simple coprocessor architecture while improving system throughput by eliminating idle periods between work items.
Data Source
AI summary
Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.