Asynchronous FIFO Buffer Using Johnson Code Write Pointer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional asynchronous data transfer systems in integrated circuits are not suitable for low latency and high bandwidth applications due to their inability to handle variable-sized data transfers across asynchronous clock domains, leading to increased latency and complexity when using binary gray code encoders.
Innovation Solution
The implementation of an asynchronous data transfer system that uses a write address generator, write pointer encoder, write pointer synchronizer, write pointer validator, read address generator, and an asynchronous FIFO buffer, which employs Johnson codes to manage write and read pointers across asynchronous clock domains, allowing for efficient transfer of variable-sized data without the need for additional auxiliary FIFO buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If binary gray code encoder is used for pointer synchronization, then pointer transfer across clock domains is achieved, but latency increases and bandwidth decreases for variable-sized data transfers
Solution Approach 1:
The patent changes the encoding parameter from binary gray code to Johnson code. This parameter change allows the system to maintain pointer transfer reliability across clock domains while enabling more efficient handling of variable-sized data transfers, thereby reducing latency and increasing bandwidth without sacrificing synchronization accuracy.
Solution Approach 2:
The patent implements dynamic pointer validation and overflow detection mechanisms that adapt to variable-sized data transfers. The system dynamically adjusts its operation based on the actual data size being transferred, allowing it to optimize performance for each transfer scenario while maintaining reliability through validation checks.
2Reliability
If binary gray code encoder is used, then pointer synchronization is maintained, but system complexity increases for variable-sized data handling
Solution Approach 1:
The patent replaces the binary gray code encoding parameter with Johnson code encoding. This change simplifies the encoder design while maintaining the essential property of single-bit transitions between consecutive values, thereby reducing device complexity without compromising synchronization accuracy across asynchronous clock domains.
Solution Approach 2:
The patent extracts and eliminates the need for complex auxiliary FIFO buffers that were required in binary gray code systems. By using Johnson code with its inherent single-bit transition property, the system removes unnecessary buffering complexity while maintaining reliable pointer synchronization.
3Adaptability or versatility
If auxiliary FIFO buffers are added to handle variable-sized data, then data transfer flexibility improves, but area requirements and complexity increase
Solution Approach 1:
The patent removes the requirement for auxiliary FIFO buffers by leveraging the properties of Johnson code encoding. The single-bit transition characteristic of Johnson code allows the system to handle variable-sized data transfers directly without needing additional buffering infrastructure, thereby reducing area requirements while maintaining transfer flexibility.
Solution Approach 2:
The Johnson code encoder serves multiple functions simultaneously: it provides pointer synchronization, enables variable-sized data transfer handling, and eliminates the need for auxiliary buffers. This multi-functionality achieves data transfer flexibility without the area overhead of additional buffering components.
Data Source
AI summary
An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.