FIFO Latency Measurement Using SysRef Markers
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Solution Overview
Problem
Circuits with multiple clock domains face challenges in synchronizing data streams and reducing latency, particularly due to uncertainties introduced by first-in first-out data structures (FIFOs) and elastic buffers, which can lead to increased power consumption and area requirements.
Innovation Solution
A method and circuit for determining FIFO latency by using a common timing reference signal (SysRef) to inject a latency marker into a FIFO coupling two clock domains, allowing for precise measurement and compensation of latency, thereby reducing the need for large buffers and minimizing additional latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large buffers are used to compensate for latency uncertainty in FIFOs, then synchronization reliability is improved, but power consumption and area requirements increase
Solution Approach 1:
The patent replaces the mechanical approach of using large physical buffers to absorb timing variations with a measurement and compensation approach. By measuring FIFO latency with markers and applying pointer adjustments, the system achieves synchronization without requiring large buffer capacities, thereby reducing power consumption and area while maintaining reliability
Solution Approach 2:
The patent changes the approach from static buffer sizing to dynamic parameter adjustment. By measuring latency and adjusting read/write pointers based on measured values, the system optimizes buffer utilization and achieves synchronization with minimal buffer requirements, reducing both power consumption and area
2Reliability
If large buffers are used to compensate for latency uncertainty in FIFOs, then synchronization reliability is improved, but area requirements increase
Solution Approach 1:
The patent replaces the mechanical approach of using large physical buffers to absorb timing variations with a measurement and compensation approach. By measuring FIFO latency with markers and applying pointer adjustments, the system achieves synchronization without requiring large buffer capacities, thereby reducing power consumption and area while maintaining reliability
Solution Approach 2:
The patent changes the approach from static buffer sizing to dynamic parameter adjustment. By measuring latency and adjusting read/write pointers based on measured values, the system optimizes buffer utilization and achieves synchronization with minimal buffer requirements, reducing both power consumption and area
3Manufacturing precision
If latency measurement and compensation mechanisms are implemented, then deterministic latency is achieved, but device complexity increases
Solution Approach 1:
The patent segments the latency compensation function into separate components: latency measurement using markers, latency calculation logic, and pointer adjustment mechanisms. This segmentation allows each component to be implemented independently and efficiently, reducing overall device complexity while achieving deterministic latency
Solution Approach 2:
The patent introduces markers as intermediary elements to measure FIFO latency. These markers serve as mediators between the transmit and receive sides, enabling latency measurement without requiring complex direct measurement circuits, thereby reducing device complexity while achieving precise latency control
4Measurement precision
If markers are used to measure FIFO latency, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces markers as intermediary elements to measure FIFO latency. These markers serve as mediators between the transmit and receive sides, enabling latency measurement without requiring complex direct measurement circuits, thereby reducing device complexity while achieving precise latency control
Solution Approach 2:
The patent uses marker copies that traverse the FIFO to measure latency. By copying marker values through the data path and comparing timestamps, the system achieves precise latency measurement using simple logic operations rather than complex measurement instrumentation
Data Source
AI summary
Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.