FIFO-division Line Buffer Clock Gating for Power Reduction
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Solution Overview
Problem
Conventional line buffers for image data processing in digital cameras face challenges in power consumption and circuit area usage, particularly when using flip-flop circuits for storing image data, as they require extensive resources and are inefficient in managing large image sizes.
Innovation Solution
The implementation of a FIFO-division system line buffer, which divides the FIFO into multiple blocks of 20 pixels each, utilizing 8 such blocks to store 160 pixels, with a clock gating circuit and a selector to manage data entry and output efficiently, reducing the number of flip-flop circuits needed and optimizing power consumption and circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If flip-flop circuits are used to store image data in a line buffer, then data storage capability is achieved, but power consumption increases significantly
Solution Approach 1:
The line buffer is divided into multiple banks (e.g., 4 banks), each containing a subset of flip-flop circuits. The clock gating circuit selectively activates only the necessary banks based on write address patterns, reducing the number of active flip-flops and thereby lowering power consumption while maintaining full data storage capability when needed.
Solution Approach 2:
The clock gating circuit implements periodic activation of flip-flop circuits based on the write address counter value. When the counter reaches a threshold (e.g., 80 out of 160), the clock signal is gated off for half the period, reducing dynamic power consumption while preserving data storage functionality through selective reactivation.
2Area of stationary object
If flip-flop circuits are mounted on the line buffer to store image data, then data storage is enabled, but the circuit area increases
Solution Approach 1:
The line buffer is segmented into multiple banks with each bank containing a portion of the total flip-flop circuits. This segmentation allows the circuit area to be distributed and managed in smaller units, reducing the concentrated area requirement while maintaining overall data storage capability through coordinated bank operation.
Solution Approach 2:
The clock gating circuit and address decoder serve multiple functions: they manage clock distribution, control power consumption, and enable selective access to different banks. This multi-functionality reduces the need for separate control circuits for each bank, thereby reducing overall circuit area while maintaining full data storage capability.
3Productivity
If a conventional line buffer structure is used, then data storage capacity is sufficient, but resource utilization is inefficient
Solution Approach 1:
The line buffer is divided into banks that can be independently activated. The address decoder and clock gating circuit intelligently select which banks to activate based on the write address pattern, ensuring that only the necessary number of flip-flop circuits are active at any given time. This improves resource utilization efficiency by reducing the number of simultaneously active flip-flops while maintaining sufficient storage capacity.
Solution Approach 2:
The system dynamically changes operational parameters (clock signal activation, bank selection) based on the data storage requirements. When full storage capacity is not needed, the system reduces the number of active flip-flops by gating the clock signal, thereby improving resource utilization efficiency while maintaining the physical capacity to store all required data when needed.
Data Source
AI summary
A semi-conductor storing apparatus is provided, which comprises plural storing units, each having a line buffer including plural flip-flop circuits and a clock supplying circuit for supplying a clock to the plural flip-flop circuits, a clock-controlling unit, which controls on/off operation of the clock supplying circuit to decide whether to output a clock, a selecting unit, which selects one from among outputs from the plural storing units, and an unit-controlling unit, which controls the operations of the clock-controlling unit and the selecting unit.